AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

ID 683132
Date 3/12/2019
Public
Document Table of Contents

Full CFP4 Channel Analysis Design Example (Excluding the Connector)

This section illustrates a full FP4 channel simulation.

Figure 68. Full Channel CFP4 Design ExampleFigure shows FPGA to CFP4 connector, excluding the connector.

The total channel length is approximately 2.4 inch from the BGA to the connector pads.

The main routing is stripline on layer 5. The connector break-out configuration is similar to what you can see at pair 2 in .

Figure 69. Full CFP4 Channel Insertion Loss PerformanceFigure excludes the CFP4 connector.
Figure 70. Full CFP4 Channel Return Loss Performance Figure excludes the CFP4 connector.

Comparing the scattering performances (SDD21 and SDD11/22) above with the host-to-module specification in CEI-28G-VSR shows that both insertion and return loss meet the specifications.

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