AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

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ID 683132
Date 3/12/2019
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Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline x
Intel® Stratix® 10 Devices and Transceiver Channels PCB Stackup Selection Guideline Recommendations for High Speed Signal PCB Routing FPGA Fan-out Region Design CFP2/CFP4 Connector Board Layout Design Guideline QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline SMA 2.4-mm Layout Design Guideline Tyco/Amphenol Interlaken Connector Design Guideline Electrical Specifications Document Revision History for AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
FPGA Fan-out Region Design x
Signal Break-out Recommendations FPGA Fan-out Region Routing Recommendations AC Coupling Capacitor Layout and Optimization Guidelines
Signal Break-out Recommendations x
Option 1: Via-In-Pad Topology Option 2: Dog-bone with GND Cutout at BGA Pad Topology Option 3: Micro-via Topology GND Cutout Under BGA Pads in Fan-out Configuration Comparison of Dog-bone with GND Cutout Under the BGA and Via-in-Pad Configurations Trace Shape Routing at the BGA Void Area (Tear Drop Configuration)
FPGA Fan-out Region Routing Recommendations x
Comparison of Conventional and Recommended Break-out Routing Topologies
Comparison of Conventional and Recommended Break-out Routing Topologies x
Conventional Jog-out Routings with Skew-matching Right After Break-out The Impact of Via Height and Via Anti-pad Over Insertion Loss
AC Coupling Capacitor Layout and Optimization Guidelines x
0201 AC Capacitor 0402 AC Capacitor PCB AC Capacitor Placement Layout Recommendation
0201 AC Capacitor x
Sweeping Anti-pad Radius Sweeping Void Width only on the First GND Plane Under the Capacitor
0402 AC Capacitor x
Sweeping Anti-pad Radius Sweeping Void Width Only on the First GND Plane under the Capacitor Adding a Trace Reference to the 0201 AC Capacitor Adding a Trace Reference to the 0402 AC Capacitor
PCB AC Capacitor Placement Layout Recommendation x
What to Avoid for AC Capacitor Configuration
CFP2/CFP4 Connector Board Layout Design Guideline x
CFP2 Host Connector, Module Assembly, and Pinout CFP4 Host Connector, Module Assembly, and Pinout Recommended PCB Design Guideline at the CFP2/CFP4 Connector CFP4 Design Example and Optimization Performance
CFP4 Design Example and Optimization Performance x
CFP4 Connector Layout: Signal Via, Trace Routing Impact, and Optimization Two Different Break-out Routings at the CFP4 Connector Area CFP4 Connector Routing Topologies Design Example Full CFP4 Channel Analysis Design Example (Excluding the Connector) CFP2 Connector Area Layout
QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline x
QSFP+ Module Assembly and Pinout Recommended PCB Design Guideline for QSFP+/zQSFP/QSFP28 Channels Recommended QSFP+ Signal Routing QSFP28 Example Design and Performance Optimization
SMA 2.4-mm Layout Design Guideline x
SMA 2.4 mm Molex® Connector Assembly PCB Design Guidelines for Channels Using the 2.4 mm Connector 2.4 mm Example Design Performance
PCB Design Guidelines for Channels Using the 2.4 mm Connector x
Recommended PCB layout Design for Version-A SMA 2.4 mm Connector Recommended PCB layout Design for Version-B SMA 2.4 mm Connector Performance Comparison between Option1 and Option2 layout Other 2.4 mm Connectors 2.4 mm Channel Specifications
Tyco/Amphenol Interlaken Connector Design Guideline x
Connector Signal and Pin Assignment
Connector Signal and Pin Assignment x
PCB Design Guidelines for Channels with 25 Gbps + Interlaken Interface Connector Recommendations Interlaken Channel Interface Performance Example
Electrical Specifications x
CEI 28 Very Short Reach (VSR) Specifications for CFP2/CFP4/QSFP+/QSFP28/zQSFP/SMA 2.4 mm Interlaken Interface Specification
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

CFP4 Connector Routing Topologies Design Example

In the figure below, notice that the CFP4 connector has not been included in simulations. The standard 24-layer stack-up at 117 mil thickness is used for this design example. The stack-up material is Megron6 and has eight signal layers and four PDR layers.

Figure 59. Proposed Design Layout Dimensions at the CFP4 Connector
Figure 60. Side and Top Views of the Design Example

The channel trace routing is on layer 5 for both of the pairs above. Pair1 has two GND cutouts (on layers 2 and 4) under the connector pads, while pair1 has only one GND cutout on layer 2.

The reason for not having a GND cutout on layer 4 for pair 2 is because trace routing needs a reference GND plane while routed and passed under the connector pads. This aids in obtaining a minimum channel path as opposed to breaking out of the opposite direction and looping back, which creates a longer channel path.

The following figures compare the performances of pair 1 and pair 2.

Figure 61. Differential Insertion Loss of Pair 1 and Pair 2
Figure 62. Differential Return Loss from the CFP4 Connector Pad
Figure 63. TDR Differential Impedance from the CFP4 Connector Pads

A quick comparison shows that pair 2 has up to 0.2 dB more insertion loss within a 15 GHz bandwidth. This is due to the lack of a GND cutout on layer 4 under the connector pads in addition to the extra routing length under the connector pads. Pair 2 also has up to 2.5 dB return loss with a 15 GHz bandwidth.

The TDR differential impedance also shows less impedance mismatch for pair 1.

In the following figure, the layout configuration has been changed from pair 2 (in the previous example) to pair 3.

Figure 64. Side and Top Views of the Design Example

In the example above, pair 3 signal vias have been moved to the left side. This allows an additional GND cutout on layer 4 for pair 2 below the CFP4 connector pads. In this configuration, pair 3 can be routed on signal layer 3. The total routing length for both pair 1 and pair 3 are now equal.

The following figures compare the performances of pair 2 and pair 3.

Figure 65. Differential Insertion Loss
Figure 66. Differential Return Loss at the CFP4 Connector Pads
Figure 67. TDR Differential Impedance at the CFP4 Connector Pads

The insertion and return loss results above show better performance for pair 2 within a 15 GHz bandwidth. This is due to a larger GND cutout below the CFP4 connector pads (combined rectangular cut out and signal via anti-pads). This is also observed from TDR differential impedance results. However, above 15 GHz, pair 2 in Figure 60 exhibits greater performance degradation than pair3 in Figure 64.

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