AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
ID
683132
Date
3/12/2019
Public
Intel® Stratix® 10 Devices and Transceiver Channels
PCB Stackup Selection Guideline
Recommendations for High Speed Signal PCB Routing
FPGA Fan-out Region Design
CFP2/CFP4 Connector Board Layout Design Guideline
QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline
SMA 2.4-mm Layout Design Guideline
Tyco/Amphenol Interlaken Connector Design Guideline
Electrical Specifications
Document Revision History for AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
Option 1: Via-In-Pad Topology
Option 2: Dog-bone with GND Cutout at BGA Pad Topology
Option 3: Micro-via Topology
GND Cutout Under BGA Pads in Fan-out Configuration
Comparison of Dog-bone with GND Cutout Under the BGA and Via-in-Pad Configurations
Trace Shape Routing at the BGA Void Area (Tear Drop Configuration)
CFP4 Host Connector, Module Assembly, and Pinout
The CFP4 module high speed electrical interface supports the following configurations:
- 4 TX lanes + 4 RX lanes, each at 25 Gbps
- 4 TX lanes + 4 RX lanes, each at 10 Gbps
Figure 52. CFP4 Host Connector Assembly and N X 25 Gbps Pin Map

The high speed electrical interface will be AC-coupled within the CFP4 module. The 25 Gbps specification is defined in the OIF-CEI-28G-VSR.
Note: For more information, refer to the CEI-28G-VSR working clause specification. Document number OIF2010.404.08.