AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

ID 683132
Date 3/12/2019
Public
Document Table of Contents

CFP4 Host Connector, Module Assembly, and Pinout

The CFP4 module high speed electrical interface supports the following configurations:

  • 4 TX lanes + 4 RX lanes, each at 25 Gbps
  • 4 TX lanes + 4 RX lanes, each at 10 Gbps
Figure 52. CFP4 Host Connector Assembly and N X 25 Gbps Pin Map

The high speed electrical interface will be AC-coupled within the CFP4 module. The 25 Gbps specification is defined in the OIF-CEI-28G-VSR.

Note: For more information, refer to the CEI-28G-VSR working clause specification. Document number OIF2010.404.08.

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