AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

ID 683132
Date 3/12/2019
Public
Document Table of Contents

Trace Shape Routing at the BGA Void Area (Tear Drop Configuration)

Impedance matching from the signal via pad to signal trace is an essential element for high speed interfaces. To avoid substantial discontinuity, Intel recommends using the following trace configuration for better transition (see the area highlighted in red).

Figure 13. Proposed tear drop configurations by PCB fabrications

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