Signal Break-out Recommendations
Figure Figure 3 shows that there are up to 4 transceiver pairs in one row for Intel® Stratix® 10 devices. Designers must assign at least 4 signals layers each separated by continuous ground planes for break-out routing. The number of layers assigned for transceivers routing is one of the key factors for stackup selection. Intel recommends that you follow FPGA break-out region guideline in the next section to achieve optimum performance.
There are three options for FPGA fan-out region routing. Each one can be selected for high speed signal routing on PCB, based on their high priority and data rate.