AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

ID 683132
Date 3/12/2019
Public
Document Table of Contents

Signal Break-out Recommendations

Figure Figure 3 shows that there are up to 4 transceiver pairs in one row for Intel® Stratix® 10 devices. Designers must assign at least 4 signals layers each separated by continuous ground planes for break-out routing. The number of layers assigned for transceivers routing is one of the key factors for stackup selection. Intel recommends that you follow FPGA break-out region guideline in the next section to achieve optimum performance.

Figure 3. Example of Recommended FPGA Break-Out Routing (Different colors stands for different layers)

There are three options for FPGA fan-out region routing. Each one can be selected for high speed signal routing on PCB, based on their high priority and data rate.

Note: Intel recommends BGA pad diameter on PCB as 20 mil for Intel® Stratix® 10 devices. This is good for pads that are not near the corners of the device. However, for those five pads which are located closest to each corner of device, the recommended pad diameter is 24 mil with 20 mil solder mask opening for inner pins and 16 mil for corner pins.

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