AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

ID 683132
Date 3/12/2019
Public
Document Table of Contents

Interlaken Channel Interface Performance Example

The channel in this example is designed for the Interlaken interface using a TYCO Interlaken connector. The board layout recommendations provided above are used in this channel design. This example design is implemented on the Intel® Arria® 10 device development kit.

A TX channel has been selected for these 3D HFSS simulations. The TX channel is routed on layer 26 using a back-drill up to layer 27. The total PCB routing is approximately 3.94 inch using stripline routing with rounded corners.

Figure 105. Stackup Layer and Material Data for the Example Interlaken ChannelThese are the specifications for the example channel:
  • 30 layers
  • Copper Foil - HVLP
  • Surface roughness = 2 µm
  • Back-drill
  • Material = Megtron6
  • Total thickness = 153.3 mil
Figure 106. Interlaken TX Channel for Simulation

The following figures show the host PCB TX channel performance from the FPGA BGA/ball to the Interlaken connector signal pads on the top layer.

Figure 107. Differential Insertion Loss on the Host PCB OnlyResults exclude the Interlaken connector.
Figure 108. Differential Return Loss from the Interlaken Connector Pads on the PCBResults exclude the Interlaken connector.

The insertion loss is below the mentioned specifications in Electrical Specifications chapter, which specifies less than 7 dB insertion loss for the host PCB.

Figure 109. Differential Measured TDR Performance for Various TX Interlaken Channels on an Arria 10 device Development KitResults show performance focused only on the PCB trace impedance and connector fan-out areas for various TX channels

Did you find the information on this page useful?

Characters remaining:

Feedback Message