AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

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ID 683132
Date 3/12/2019
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Document Table of Contents x
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline x
Intel® Stratix® 10 Devices and Transceiver Channels PCB Stackup Selection Guideline Recommendations for High Speed Signal PCB Routing FPGA Fan-out Region Design CFP2/CFP4 Connector Board Layout Design Guideline QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline SMA 2.4-mm Layout Design Guideline Tyco/Amphenol Interlaken Connector Design Guideline Electrical Specifications Document Revision History for AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
FPGA Fan-out Region Design x
Signal Break-out Recommendations FPGA Fan-out Region Routing Recommendations AC Coupling Capacitor Layout and Optimization Guidelines
Signal Break-out Recommendations x
Option 1: Via-In-Pad Topology Option 2: Dog-bone with GND Cutout at BGA Pad Topology Option 3: Micro-via Topology GND Cutout Under BGA Pads in Fan-out Configuration Comparison of Dog-bone with GND Cutout Under the BGA and Via-in-Pad Configurations Trace Shape Routing at the BGA Void Area (Tear Drop Configuration)
FPGA Fan-out Region Routing Recommendations x
Comparison of Conventional and Recommended Break-out Routing Topologies
Comparison of Conventional and Recommended Break-out Routing Topologies x
Conventional Jog-out Routings with Skew-matching Right After Break-out The Impact of Via Height and Via Anti-pad Over Insertion Loss
AC Coupling Capacitor Layout and Optimization Guidelines x
0201 AC Capacitor 0402 AC Capacitor PCB AC Capacitor Placement Layout Recommendation
0201 AC Capacitor x
Sweeping Anti-pad Radius Sweeping Void Width only on the First GND Plane Under the Capacitor
0402 AC Capacitor x
Sweeping Anti-pad Radius Sweeping Void Width Only on the First GND Plane under the Capacitor Adding a Trace Reference to the 0201 AC Capacitor Adding a Trace Reference to the 0402 AC Capacitor
PCB AC Capacitor Placement Layout Recommendation x
What to Avoid for AC Capacitor Configuration
CFP2/CFP4 Connector Board Layout Design Guideline x
CFP2 Host Connector, Module Assembly, and Pinout CFP4 Host Connector, Module Assembly, and Pinout Recommended PCB Design Guideline at the CFP2/CFP4 Connector CFP4 Design Example and Optimization Performance
CFP4 Design Example and Optimization Performance x
CFP4 Connector Layout: Signal Via, Trace Routing Impact, and Optimization Two Different Break-out Routings at the CFP4 Connector Area CFP4 Connector Routing Topologies Design Example Full CFP4 Channel Analysis Design Example (Excluding the Connector) CFP2 Connector Area Layout
QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline x
QSFP+ Module Assembly and Pinout Recommended PCB Design Guideline for QSFP+/zQSFP/QSFP28 Channels Recommended QSFP+ Signal Routing QSFP28 Example Design and Performance Optimization
SMA 2.4-mm Layout Design Guideline x
SMA 2.4 mm Molex® Connector Assembly PCB Design Guidelines for Channels Using the 2.4 mm Connector 2.4 mm Example Design Performance
PCB Design Guidelines for Channels Using the 2.4 mm Connector x
Recommended PCB layout Design for Version-A SMA 2.4 mm Connector Recommended PCB layout Design for Version-B SMA 2.4 mm Connector Performance Comparison between Option1 and Option2 layout Other 2.4 mm Connectors 2.4 mm Channel Specifications
Tyco/Amphenol Interlaken Connector Design Guideline x
Connector Signal and Pin Assignment
Connector Signal and Pin Assignment x
PCB Design Guidelines for Channels with 25 Gbps + Interlaken Interface Connector Recommendations Interlaken Channel Interface Performance Example
Electrical Specifications x
CEI 28 Very Short Reach (VSR) Specifications for CFP2/CFP4/QSFP+/QSFP28/zQSFP/SMA 2.4 mm Interlaken Interface Specification
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

The Impact of Via Height and Via Anti-pad Over Insertion Loss

This section demonstrates how much via length and anti-pad size change the insertion loss. The results of this examination are based on the following criteria:

  • A 24-layer stackup
  • A via-in-pad with a 10 mil drill (finished size) hole
  • 18 mil pad
Figure 34. 24-Layer Stack-up Information for investigations on insertion loss impact using various via lengths and anti-pad sizes.
Figure 35. Differential Via and Anti-pad Configuration
Table 3.  Impact of Via Length on Insertion LossIn this case, the anti-pad (GND cutout for each GND layer up to the backdrill) is fixed at 95 mil x 28 mil.
Case Insertion Loss @ 14 GHz Return Loss @14 GHz, ~ dB
Via length from top to L3 (7.4 mil) -0.1730 dB -29
Via length from top to L5 (16.6 mil) -0.1768 dB -28
Via length from top to L7 (25.8 mil) -0.1828 dB -27
Figure 36. Impact on Differential Insertion Loss by Via Length (SDD21)
Figure 37. Impact on Differential Return Loss by Via Length (SDD11)
Table 4.  Impact of Via Anti-pad Length on Insertion LossThe via length from the top to layer 3 is 7.4 mil.
Case GND02 Cutout Size GND04 Cutout Size IL 14 GHz
1A 68 mil x 28 mil 68 mil x 28 mil -0.1988 dB
2A 95 mil x 28 mil 95 mil x 28 mil -0.1730 dB
Table 5.  Impact of Via Anti-pad Width on Insertion LossFor various GND cutouts or (or anti-pad), the via length from the top to layer 5 is 16.6 mil.
Case/Cutout GND02 GND04 GND06 IL @14 GHz
1B 95 mil x 28 mil 95 mil x 28 mil 95 mil x 28 mil -0.1768 dB
2B 95 mil x 50 mil 95 mil x 50 mil 95 mil x 50 mil -0.1741 dB

The signal anti-pad size results in these tables demonstrates that the larger the anti-pad, the less insertion and return loss results. Because space is always a consideration, you must balance the signal anti-pad size with the need for proper break-out routing.

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