AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

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ID 683132
Date 3/12/2019
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Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline x
Intel® Stratix® 10 Devices and Transceiver Channels PCB Stackup Selection Guideline Recommendations for High Speed Signal PCB Routing FPGA Fan-out Region Design CFP2/CFP4 Connector Board Layout Design Guideline QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline SMA 2.4-mm Layout Design Guideline Tyco/Amphenol Interlaken Connector Design Guideline Electrical Specifications Document Revision History for AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
FPGA Fan-out Region Design x
Signal Break-out Recommendations FPGA Fan-out Region Routing Recommendations AC Coupling Capacitor Layout and Optimization Guidelines
Signal Break-out Recommendations x
Option 1: Via-In-Pad Topology Option 2: Dog-bone with GND Cutout at BGA Pad Topology Option 3: Micro-via Topology GND Cutout Under BGA Pads in Fan-out Configuration Comparison of Dog-bone with GND Cutout Under the BGA and Via-in-Pad Configurations Trace Shape Routing at the BGA Void Area (Tear Drop Configuration)
FPGA Fan-out Region Routing Recommendations x
Comparison of Conventional and Recommended Break-out Routing Topologies
Comparison of Conventional and Recommended Break-out Routing Topologies x
Conventional Jog-out Routings with Skew-matching Right After Break-out The Impact of Via Height and Via Anti-pad Over Insertion Loss
AC Coupling Capacitor Layout and Optimization Guidelines x
0201 AC Capacitor 0402 AC Capacitor PCB AC Capacitor Placement Layout Recommendation
0201 AC Capacitor x
Sweeping Anti-pad Radius Sweeping Void Width only on the First GND Plane Under the Capacitor
0402 AC Capacitor x
Sweeping Anti-pad Radius Sweeping Void Width Only on the First GND Plane under the Capacitor Adding a Trace Reference to the 0201 AC Capacitor Adding a Trace Reference to the 0402 AC Capacitor
PCB AC Capacitor Placement Layout Recommendation x
What to Avoid for AC Capacitor Configuration
CFP2/CFP4 Connector Board Layout Design Guideline x
CFP2 Host Connector, Module Assembly, and Pinout CFP4 Host Connector, Module Assembly, and Pinout Recommended PCB Design Guideline at the CFP2/CFP4 Connector CFP4 Design Example and Optimization Performance
CFP4 Design Example and Optimization Performance x
CFP4 Connector Layout: Signal Via, Trace Routing Impact, and Optimization Two Different Break-out Routings at the CFP4 Connector Area CFP4 Connector Routing Topologies Design Example Full CFP4 Channel Analysis Design Example (Excluding the Connector) CFP2 Connector Area Layout
QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline x
QSFP+ Module Assembly and Pinout Recommended PCB Design Guideline for QSFP+/zQSFP/QSFP28 Channels Recommended QSFP+ Signal Routing QSFP28 Example Design and Performance Optimization
SMA 2.4-mm Layout Design Guideline x
SMA 2.4 mm Molex® Connector Assembly PCB Design Guidelines for Channels Using the 2.4 mm Connector 2.4 mm Example Design Performance
PCB Design Guidelines for Channels Using the 2.4 mm Connector x
Recommended PCB layout Design for Version-A SMA 2.4 mm Connector Recommended PCB layout Design for Version-B SMA 2.4 mm Connector Performance Comparison between Option1 and Option2 layout Other 2.4 mm Connectors 2.4 mm Channel Specifications
Tyco/Amphenol Interlaken Connector Design Guideline x
Connector Signal and Pin Assignment
Connector Signal and Pin Assignment x
PCB Design Guidelines for Channels with 25 Gbps + Interlaken Interface Connector Recommendations Interlaken Channel Interface Performance Example
Electrical Specifications x
CEI 28 Very Short Reach (VSR) Specifications for CFP2/CFP4/QSFP+/QSFP28/zQSFP/SMA 2.4 mm Interlaken Interface Specification
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

Connector Signal and Pin Assignment

Intel recommends the TE Connectivity® 3.9 mm STRADA Whisper connector (R/A receptacle) or IMPACT connector for the 25+ Interlaken interface. This connector is ideal for cabled connections. The part number is TYCO 2187194-1. This connector can handle both TX and RX signals. The cable assembly crosses the signal to provide connectivity from TX to RX and from RX to TX. A single connector supports up to 24 channels (24 TX and 24 RX). The advantage of this connector is that it can operate up to 57.8 Gbps with no skew in pair.

Figure 98. Interlaken Single or Dual Connector Setups

The single connector allows up to 22 lanes of high-speed differential connectivity to another board for interoperability. The Interlaken Alliance currently specifies only 20 lanes are needed for interoperability.

The dual connector setup allows up to 44 lanes of high-speed differential connectivity to another board. In this case, the Interlaken Alliance currently specifies the need for only 40 lanes for interoperability. The connector and cable assembly are rated to support data rates up to 28.9 Gbps with non-return to zero (NRZ) encoding.

Note: TX[20:21] and RX[20:21] are spare lanes that you can use for other cases where extra lanes may be required.
Figure 99. Connector Signal Pin Assignment and Magnified View of Signal PinsPin assignments for the high-speed differential pairs. Signals labeled TX are outputs from the board, while RX signals are inputs to the board.

The cable assembly connecting each PCB's on-board connector(s) (STRADA Whisper connectors to R/A receptacles) takes care of swapping TX to RX. Therefore, the connector pinouts are identical on either inter operating board.

Note: TX_REFCK_P/N and RX_REFCK_PN are not provided for high-speed physical interoperability.

The insertion loss of the connector is less than 1 dB and is linear up to 20 GHz. For an 85 Ω channel, Intel recommends that you use the 85 Ω version of the connector. Likewise, for a 100 Ω channel, Intel recommends that you use the 100 Ω version of the connector. There is little to no skew through the high-speed differential pairs within the connector.

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