AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

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ID 683132
Date 3/12/2019
Public
Document Table of Contents
Document Table of Contents
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
Intel® Stratix® 10 Devices and Transceiver Channels PCB Stackup Selection Guideline Recommendations for High Speed Signal PCB Routing FPGA Fan-out Region Design CFP2/CFP4 Connector Board Layout Design Guideline QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline SMA 2.4-mm Layout Design Guideline Tyco/Amphenol Interlaken Connector Design Guideline Electrical Specifications Document Revision History for AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
FPGA Fan-out Region Design
Signal Break-out Recommendations FPGA Fan-out Region Routing Recommendations AC Coupling Capacitor Layout and Optimization Guidelines
Signal Break-out Recommendations
Option 1: Via-In-Pad Topology Option 2: Dog-bone with GND Cutout at BGA Pad Topology Option 3: Micro-via Topology GND Cutout Under BGA Pads in Fan-out Configuration Comparison of Dog-bone with GND Cutout Under the BGA and Via-in-Pad Configurations Trace Shape Routing at the BGA Void Area (Tear Drop Configuration)
FPGA Fan-out Region Routing Recommendations
Comparison of Conventional and Recommended Break-out Routing Topologies
Comparison of Conventional and Recommended Break-out Routing Topologies
Conventional Jog-out Routings with Skew-matching Right After Break-out The Impact of Via Height and Via Anti-pad Over Insertion Loss
AC Coupling Capacitor Layout and Optimization Guidelines
0201 AC Capacitor 0402 AC Capacitor PCB AC Capacitor Placement Layout Recommendation
0201 AC Capacitor
Sweeping Anti-pad Radius Sweeping Void Width only on the First GND Plane Under the Capacitor
0402 AC Capacitor
Sweeping Anti-pad Radius Sweeping Void Width Only on the First GND Plane under the Capacitor Adding a Trace Reference to the 0201 AC Capacitor Adding a Trace Reference to the 0402 AC Capacitor
PCB AC Capacitor Placement Layout Recommendation
What to Avoid for AC Capacitor Configuration
CFP2/CFP4 Connector Board Layout Design Guideline
CFP2 Host Connector, Module Assembly, and Pinout CFP4 Host Connector, Module Assembly, and Pinout Recommended PCB Design Guideline at the CFP2/CFP4 Connector CFP4 Design Example and Optimization Performance
CFP4 Design Example and Optimization Performance
CFP4 Connector Layout: Signal Via, Trace Routing Impact, and Optimization Two Different Break-out Routings at the CFP4 Connector Area CFP4 Connector Routing Topologies Design Example Full CFP4 Channel Analysis Design Example (Excluding the Connector) CFP2 Connector Area Layout
QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline
QSFP+ Module Assembly and Pinout Recommended PCB Design Guideline for QSFP+/zQSFP/QSFP28 Channels Recommended QSFP+ Signal Routing QSFP28 Example Design and Performance Optimization
SMA 2.4-mm Layout Design Guideline
SMA 2.4 mm Molex® Connector Assembly PCB Design Guidelines for Channels Using the 2.4 mm Connector 2.4 mm Example Design Performance
PCB Design Guidelines for Channels Using the 2.4 mm Connector
Recommended PCB layout Design for Version-A SMA 2.4 mm Connector Recommended PCB layout Design for Version-B SMA 2.4 mm Connector Performance Comparison between Option1 and Option2 layout Other 2.4 mm Connectors 2.4 mm Channel Specifications
Tyco/Amphenol Interlaken Connector Design Guideline
Connector Signal and Pin Assignment
Connector Signal and Pin Assignment
PCB Design Guidelines for Channels with 25 Gbps + Interlaken Interface Connector Recommendations Interlaken Channel Interface Performance Example
Electrical Specifications
CEI 28 Very Short Reach (VSR) Specifications for CFP2/CFP4/QSFP+/QSFP28/zQSFP/SMA 2.4 mm Interlaken Interface Specification
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

Comparison of Dog-bone with GND Cutout Under the BGA and Via-in-Pad Configurations

Figure 10. Comparison of TDR from the FPGA Pad of Via-in-Pad and Dog-bone ConfigurationsThe pink line indicates the dog-bone configuration and the green line indicates the via-in-pad configuration.

In terms of TDR, both configurations have similar performance.

Figure 11. Full channel scattering parameter performances for Dog-Bone Configuration with GND/Void cutout underneath of BGA (Option 2) vs Via-in-pad (Option 1) ConfigurationsFigure shows the identical channel but uses the via-in-pad or dog-bone configuration in the FPGA area.
Note:
  • Option 1 (Green): Via-in-pad.
  • Option 2 (Pink): Dog-bone with GND/Void cutout under BGA pad configuration.

In this example, the via-in-pad shows slightly better performance. The other advantage of via-in-pad is that it provides more space for fan-out routing.

Figure 12. TDR Performance and TL Impedance ImpactThe example uses a dog-bone fan-out configuration and one layer GND cutout under the BGA pad by various TL routing impedances.

This example shows that slightly lowering the TL routing impedance ensures a smoother transition from the BGA pad, which results in less reflection on the channel. Intel recommends a 95Ω TL routing impedance for high speed serial interface (HSSI) channels.

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