AN 915: JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel Stratix® 10 E-Tile Devices

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ID 683559
Date 11/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B Intel® FPGA IP and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 915: JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices

1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices

The JESD204B Intel® FPGA IP is a high-speed point-to-point serial interface intellectual property (IP).

The JESD204B Intel® FPGA IP has been hardware-tested with a number of selected JESD204B-compliant analog-to-digital converter (ADC) devices.

This report highlights the interoperability of the JESD204B Intel® FPGA IP using E-tile transceivers with the AD9208 converter evaluation module (EVM) from Analog Devices Inc. (ADI). The following sections describe the hardware checkout methodology and test results.


Section Content
Hardware Requirements
Hardware Setup
Hardware Checkout Methodology
JESD204B Intel FPGA IP and ADC Configurations
Test Results
Test Result Comments
Document Revision History for AN 915: JESD204B Intel FPGA IP and ADI AD9208 Interoperability Report for Intel Stratix 10 E-Tile Devices
Appendix

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