AN 915: JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel Stratix® 10 E-Tile Devices

Download PDF
ID 683559
Date 11/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B Intel® FPGA IP and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 915: JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices

1.3.2. Receiver Transport Layer

To check the data integrity of the payload data stream through the JESD204B Intel® FPGA IP core receiver and transport layer, the ADC is configured to output PRBS-9 and Ramp test data pattern. The ADC is also set to operate with the same configuration as set in the JESD204B Intel® FPGA IP core. The PRBS checker/Ramp checker in the FPGA fabric checks data integrity for one minute.

This figure shows the conceptual test setup for data integrity checking.

Figure 3. Data Integrity Check Using PRBS/Ramp Checker
Table 3.  Transport Layer Test Cases
Test Case Objective Description Passing Criteria

TL.1

 Check the transport layer mapping using Ramp test pattern.

Read err_status register from avs_reg_map with test duration of 1 minute.

Bit 0 of the register is a sticky bit from pattern checker and indicates pass or fail status of data validation.

The following signal in <ip_variant_name>.sv is tapped:

  • jesd204_rx_data_valid

For the signal specified above, rxlink_clk is used as the sampling clock for the Signal Tap.

The following signal in altera_jesd204_transport_rx_top.sv is tapped:

  • jesd204_rx_data_valid

The rxframe_clk is used as the sampling clock for the Signal Tap.

  • The jesd204_rx_data_valid signal is asserted.
  • The jesd204_rx_int signal is deasserted.
  • Bit 0 of the err_status is read zero.

TL.2

 Check the transport layer mapping using PRBS-9 test pattern.

Read err_status register from avs_reg_map with test duration of 1 minute.

Bit 0 of the register is a sticky bit from pattern checker and indicates pass or fail status of data validation.

The following signal in <ip_variant_name>.sv is tapped:

  • jesd204_rx_data_valid

For the signal specified above, rxlink_clk is used as the sampling clock for the Signal Tap.

The following signal in altera_jesd204_transport_rx_top.sv is tapped:

  • jesd204_rx_data_valid

The rxframe_clk is used as the sampling clock for the Signal Tap.

  • The jesd204_rx_data_valid signal is asserted.
  • The jesd204_rx_int signal is deasserted.
  • Bit 0 of the err_status is read zero.
Level Two Title