AN 915: JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel Stratix® 10 E-Tile Devices

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ID 683559
Date 11/29/2021
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B Intel® FPGA IP and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 915: JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices

1.3.3. Descrambling

The PRBS/Ramp checker at the receiver transport layer checks the data integrity of descrambler.

The Signal Tap Logic Analyzer tool monitors the operation of the receiver transport layer.

Table 4.  Descrambler Test Cases
Test Case Objective Description Passing Criteria
SCR.1 Check the functionality of the descrambler using Ramp test pattern.

Enable scrambler at the ADC and descrambler at the JESD204B Intel® FPGA IP core receiver.

The signals that are tapped in this test case are similar to test case TL.1.
  • The jesd204_link_data_valid signal is asserted.
  • The jesd204_rx_int signal is deasserted.
  • Bit 0 of the err_status register is read zero.

SCR.2

 Check the functionality of the descrambler using PRBS-9 test pattern.

Enable scrambler at the ADC and descrambler at the JESD204B Intel® FPGA IP core receiver.

The signals that are tapped in this test case are similar to test case TL.2
  • The jesd204_link_data_valid signal is asserted.
  • The jesd204_rx_int signal is deasserted.
  • Bit 0 of the err_status register is read zero.
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