AN 915: JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel Stratix® 10 E-Tile Devices

ID 683559
Date 11/29/2021
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1.6. Test Result Comments

In each test case, the JESD204B receiver IP core successfully initialize from CGS phase, ILA phase, and until user data phase.

No data integrity issue is observed by the PRBS and Ramp checker for all JESD configurations.

In the deterministic latency measurement, consistent total latency is observed across multiple power cycles and resets.

For a few JESD configurations, to avoid lane deskew error or achieve deterministic latency on FPGA, RBD offset/LMFC offset register needs to be programmed. The modes and the corresponding values used are tabled below.
Mode (LMF) SCR csr_rbd_offset (syncn_sysref_ctrl [10:3]) csr_lmfc_offset

(syncn_sysref_ctrl [19:12])

112 – K16 0/1 N/A 4
211 – K32 0/1 0x7 N/A
211 – K20 0/1 0x3 0x15
211 – K16 0/1 0x7 N/A
411 – K20 0/1 N/A 0x2
811 – K32 0/1 0x5 N/A
811 – K20 1 0x2 0x2
812 – K32 0/1 0xD N/A
812 – K16 0/1 0x5 N/A
222 – K16 0/1 N/A 0x4
421 – K20 0/1 0x4 N/A
821 – K20 0/1 N/A 0x2
148 – K32 0/1 0x3F N/A
148 – K16 0/1 0x1F N/A
244 – K16 0/1 0xF N/A
841 – K20 0/1 N/A 0x1
288 – K16 0/1 0x1F N/A
5 The JESD mode gives consistent latency even without LMFC offset, but the LMFC offset is still used to reduce the latency value.