AN 915: JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel Stratix® 10 E-Tile Devices

ID 683559
Date 11/29/2021
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1.8. Appendix

Device Used and Quartus Tool Version

The Intel® Quartus® Prime Pro Edition software version 19.4 Build 64 is used for compilation of designs.

Additional JESD modes supported by ADC

The modes enlisted here have not been validated in this interoperability test, but they are supported by the ADC. These have been tabulated here for future reference.

L M F S N N' Comments
1 8 16 1 14 16 F=16 configuration is not supported by transport layer of Intel FPGA example design.
1 1 1 1 8 8

N’=8 configuration is not supported by transport layer of Intel FPGA example design.

1 1 2 2 8 8
2 1 1 2 8 8
2 1 2 4 8 8
2 1 4 8 8 8
4 1 1 4 8 8
4 1 2 8 8 8
1 2 2 1 8 8
2 2 1 1 8 8
2 2 2 2 8 8
4 2 1 2 8 8
4 2 2 4 8 8
4 2 4 8 8 8