AN 915: JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel Stratix® 10 E-Tile Devices

ID 683559
Date 11/29/2021

1.3.4. Deterministic Latency (Subclass 1)

The figure below shows the block diagram of deterministic latency test setup. AD9528 clock generator on the EVM provides a periodic SYSREF pulse for both the AD9208 and JESD204B Intel® FPGA IP core. The SYSREF generator is running in the link clock domain and the period of SYSREF pulse is configured to the desired multiframe size. The SYSREF pulse restarts the LMF counter and realigns it to the Local Multi Frame Clocks (LMFC) boundary.

Figure 4. Deterministic Latency Test Setup Block Diagram

The deterministic latency measurement block checks deterministic latency by measuring the number of link clock counts between the start of de-assertion of SYNC~ to the first user data output.

Figure 5. Deterministic Latency Measurement Timing Diagram

With the setup above, three test cases were defined to prove deterministic latency. The JESD204B Intel® FPGA IP core does continuous SYSREF detection.

Table 5.  Deterministic Latency Test Cases
Test Case Objective Description Passing Criteria

Check the FPGA SYSREF single detection.

Check that the FPGA detects the first rising edge of SYSREF pulse.

Read the status of sysref_singledet (bit[2]) identifier in syncn_sysref_ctrl register at address 0x54.

Read the status of csr_sysref_lmfc_ err (bit[1]) identifier in the rx_err0 register at address 0x60.

The value of sysref_singledet identifier should be zero.

The value of csr_sysref_lmfc_err identifier should be zero.

DL.2 Check the SYSREF capture. Check that FPGA and ADC capture SYSREF correctly and restart the LMF counter. Both FPGA and ADC are also repetitively reset.

Read the value of rbd_count (bit[10:3]) identifier in rx_status0 register at address 0x80.

If the SYSREF is captured correctly and the LMF counter restarts, for every reset, the rbd_count value should only drift within 1-2 link clocks due to word alignment.
DL.3 Check the latency from start of SYNC~ deassertion to first user data output. Check that the latency is fixed across multiple resets and power cycle of both FPGA and ADC.

Record the number of link clocks count from the start of SYNC~ deassertion to the first user data output, which is the assertion of jesd204_rx_link_valid signal. The deterministic latency measurement block in Figure 4 has a counter to measure the link clock count.

Consistent latency from the start of SYNC~ deassertion to the assertion of jesd204_rx_link_valid signal.