AN 915: JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel Stratix® 10 E-Tile Devices

ID 683559
Date 11/29/2021
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1.2. Hardware Setup

An Intel® Stratix® 10 TX Signal Integrity (SI) Development Kit (Production Rev B Edition) is used with the ADI AD9208 daughter card module installed to the development board’s FMC+ connector.

  • The AD9208 EVM derives power from Intel® Stratix® 10 TX SI Development Kit through FMC+ pins.
  • The FPGA clock is supplied by a Silicon Labs Si5341 clock generator and the sampling clock to the ADC AD9208 EVM is given by external clock source ADF4355.
  • The ADF4355 derives reference clock from the Si5341 clock generator.
  • For Subclass 1, the FPGA generates SYSREF for the JESD204B Intel® FPGA IP core as well as the AD9208 device.
  • SYSREF is provided to the ADC through SMA connector.
Note: Intel® recommends that SYSREF to be provided by the clock generator that sources the transceiver reference clock to FPGA, core reference clock to FPGA, and sampling clock to ADC.
Figure 1. Hardware Setup
Figure 2. System DiagramThis system-level diagram shows how the different modules connect.

In this setup, where LMF = 882, the data rate of the transceiver lanes is 16.0 Gbps. The Si5341 chip in the Intel® Stratix® 10 EVM provides 400 MHz transceiver reference clock to FPGA, 400 MHz core reference clock to the FPGA, and 200 MHz input clock to ADF4355 EVM. ADF4355EVM provides 1600 MHz sampling clock to AD9208 device. A periodic SYSREF is generated by the FPGA and provided to the ADC through the SMA connector. The AD9208 device is configured in SYSREF N-shot mode and JESD204B Intel® FPGA IP in FPGA is configured in SYSREF continuous mode for complete testing of this report. The JESD204B Intel® FPGA IP core is instantiated in Duplex mode but only the receiver path is used.