AN 915: JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel Stratix® 10 E-Tile Devices

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ID 683559
Date 11/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B Intel® FPGA IP and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 915: JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices

1.3.1.1. Code Group Synchronization

Table 1.  CGS Test Cases
Test Case Objective Description Passing Criteria

CGS.1

Check whether sync request is de-asserted after correct reception of four successive /K/ characters.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_rx_pcs_data[(L*32)-1:0]
  • jesd204_rx_pcs_data_valid[L-1:0]
  • jesd204_rx_pcs_kchar_data[(L*4)-1:0] 1

The following signals in <ip_variant_name>.v are tapped:

  • rx_dev_sync_n
  • jesd204_rx_int

The rxlink_clk signal is used as the sampling clock for the Signal Tap logic analyzer.

Each lane is represented by a 32-bit data bus for the jesd204_rx_pcs_data signal. The 32-bit data bus is divided into four octets of the corresponding lane.

  • The /K/ character or K28.5 (0xBC) is transmitted at each octet of the jesd204_rx_pcs_data bus.
  • The jesd204_rx_pcs_data_valid signal is asserted to indicate data from the PCS is valid.
  • The jesd204_rx_pcs_kchar_data signal is asserted whenever control characters such as the /K/, /R/, /Q/, or /A/ characters are observed.
  • The rx_dev_sync_n signal is deasserted after correct reception of at least four successive /K/ characters.
  • The jesd204_rx_int signal is deasserted if there is no error.

CGS.2

Check full CGS at the receiver after correct reception of another four 8B/10B characters.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_rx_pcs_errdetect[(L*4)-1:0]
  • jesd204_tx_pcs_disperr[(L*4)-1:0] 1

The following signal in <ip_variant_name>.v is tapped:

  • jesd204_rx_int

The rxlink_clk signal is used as the sampling clock for the Signal Tap logic analyzer.

  • The jesd204_rx_pcs_errdetect, jesd204_rx_pcs_disperr, and jesd204_rx_int signals should not be asserted after jesd204_rx_pcs_data_valid signal assertion.
1 L is the number of lanes.
Level Two Title