1. Intel Agilex® 7 Power Distribution Network Design Guidelines Overview
In the previous FPGA families (for example, the Intel® Stratix® 10 and Intel® Arria® 10 devices), the PDN tool was used along with power consumption data from the Early Power Estimator (EPE) and the pin connection guidelines to design and optimize board-level PDN. However, due to achieving non-feasible PDN design tool (decoupling capacitors) specifically for core, and with pessimistic results, the PDN tool is not used or supported for the Intel Agilex® 7 device family.
The information in this application note is intended to provide guidelines to allow you to successfully complete your PDN design, without requiring additional support.
Did you find the information on this page useful?