AN 910: Intel Agilex Power Distribution Network Design Guidelines

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ID 683393
Date 6/02/2022
Public
Document Table of Contents

1. Intel® Agilex™ Power Distribution Network Design Guidelines Overview

This application note provides information for the Intel® Agilex™ device family power distribution network (PDN) design guidelines. A solid design guidelines for the Intel® Agilex™ device family PDN including fixed decoupling capacitors on board and minimum simulation is proposed.

In the previous FPGA families (for example, the Intel® Stratix® 10 and Intel® Arria® 10 devices), the PDN tool was used along with power consumption data from the Early Power Estimator (EPE) and the pin connection guidelines to design and optimize board-level PDN. However, due to achieving non-feasible PDN design tool (decoupling capacitors) specifically for core, and with pessimistic results, the PDN tool is not used or supported for the Intel® Agilex™ device family.

The information in this application note is intended to provide guidelines to allow you to successfully complete your PDN design, without requiring additional support.

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