2.3.3. Power Nets and Transient Specifications
Rail transient provided in the Table 11 is used to design and simulate the board level. Choose the recommended load slew rates and step load at FPGA package ball below for PCB-level PDN system simulations and design. Table 11 shows the maximum tolerable step load at FPGA package pin. The recommended step load in Table 11 is connected to FPGA package ball along with the PCB post-layout model (with decoupling capacitors and voltage regulator model excluding package and silicon/die model) in an EDA tool for time domain simulation to meet rail tolerance of respective power net in Table 10 at FPGA package ball.
Table 11 shows for the recommended step load at package ball and step load’s slew rate.
|Package Power Rails||At Package Balls (Step Load)||DI/dt at Package Balls (for Board Design)-Slew Rate||Notes|
|DI (A)-Step Load||DI/dt (A/µs)-Slew Rate|
|VCC/VCCP Core: AGF006/AGF008||4||20||The step load is the worst step load in the design based on 80% core utilization, 80% DSP, and 30% M20K utilization. The toggling rate is assumed to be 15%.|
|VCC/VCCP Core: AGF012/AGF014||17||200||The step load is the worst step load in the design based on 80% core utilization, 80% DSP, and 30% M20K utilization. The toggling rate is assumed to be 15%.|
|VCC/VCCP Core: AGF012/AGF014 (low power scenario)||12||141||Low power scenario case, maximum current at 70 A.|
|VCC/VCCP Core: AGF019/AGF023 and AGI019/AGI023||30.5||305||The step load is the worst step load in the design based on 80% core utilization, 80% DSP, and 30% M20K utilization. The toggling rate is assumed to be 15%.|
|VCC/VCCP Core: AGF027/AGF022 and AGI027/AGI022||32.5||325|
|VCC/VCCP Core: AGI035/AGI040||7||269|
|VCC/VCCP Core: AGI041||21||420|
|VCC/VCCP Core: AGM039/AGM032||23||742|
|VCCPT (low power scenario)||0.22||1.1||Low power scenario case, maximum current at 0.8 A.|
|VCCIO_PIO||0.645||10.8||Current specification is per I/O bank. Each I/O bank consists of 96 x I/Os. More I/O banks can join the same voltage regulator but current specification stays per I/O bank.|
|VCCH||1.12||4.8||Step current at package ball per each AIB Bridge. The number of AIB Bridge is calculated based on number of tiles in package.|
|VCCRT_GXE (low power scenario)||0.44||5.86||Per 2 quads of E-Tile, low power scenario case, maximum current at 3 A.|
|VCC_HSSI_GXP (low power scenario)||1.0||10||Per P-Tile, low power scenario case, maximum current at 3.5 A.|
|VCCRT_GXP||1.56||14.85||Slowest step load but largest current amplitude. Per P-Tile.|
|VCCRT_GXP (low power scenario)||0.3||6||Per 2 quads of P-Tile, low power scenario case, maximum current at 1.5 A.|
|VCCH_GXP (low power scenario)||0.2||50||Per P-Tile, low power scenario case, maximum current at 0.7 A.|
|VCCERT_FGT_GXF||0.228||22.8||Per single FGT—F-Tile channel|
|0.935||1.33||For 8 x FGT—F-Tile channels|
|1.87||1.24||For 16 x FGT—F-Tile channels|
|VCCH_FGT_GXF||0.031||31||Per single FGT—F-Tile channel|
|0.18||0.26||For 8 x FGT—F-Tile channels|
|0.37||0.25||For 16 x FGT—F-Tile channels|
|VCCERT2_FHT_GXF||0.03||0.49||Per single FHT—F-Tile channel|
|0.128||0.43||For 4 x FHT—F-Tile channels|
|VCCERT1_FHT_GXF||0.207||3.04||Per single FHT—F-Tile channel|
|0.785||2.62||For 4 x FHT—F-Tile channels|
|VCCEHT_FHT_GXF||0.022||0.35||Per single FHT—F-Tile channel|
|0.064||0.21||For 4 x FHT—F-Tile channels|
You must also notice the following:
- Step current at package pin is only provided for critical power rails due to either having high current/power profile at die or being highly sensitive. Intel® recommends you to do transient/time domain PDN simulation by using this step load for these critical power rails in Table 11 to ensure you will meet the voltage specification at package pin. If the voltage specification is not met at package pin, decoupling capacitors must be adjusted.
- Intel® do not provide step current for other power rails not mentioned in Table 11. Those power rails are called non-critical power rail due to having less sensitivity or low current profile/power consumption at silicon. Intel® do not recommend time domain PDN analysis for non-critical power rails. Non-critical power rails PDN design suggested in this application note is guaranteed.
- Intel® recommends you to perform DC IR drop analysis for all power rails.