1. Agilex™ 7 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused Tiles
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Agilex™ 7 Device Family PDN Design Summary
9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines
2.1.2.1. Recommended Power Tree for the Agilex™ 7 Devices with only P-Tile and E-Tile in the Device Packages
2.1.2.2. Recommended Power Tree for the Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.1.2.3. Recommended Power Tree for the Agilex™ 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.4.1. Agilex™ 7 FPGA Packages Board-Level Decoupling Capacitors Summary
2.4.2. Agilex™ 7 E-Tile Decoupling Capacitors Summary per Tile Agilex™ 7 E-Tile Board-Level Decoupling Capacitors Summary
2.4.3. Agilex™ 7 P-Tile Board-Level Decoupling Capacitors Summary
2.4.4. Agilex™ 7 F-Tile Board-Level Decoupling Capacitors Summary
2.4.5. Agilex™ 7 R-Tile Board-Level Decoupling Capacitors Summary
2.1.1. Power Budget
Use the Intel® FPGA Power and Thermal Calculator (PTC) to determine the power for your applications. Scale the recommended decoupling capacitors based on the scaling factor of the exact power consumption to the maximum power consumption.
The rule of thumb is to scale the number of suggested decoupling capacitors. For example, if your scale factor is 2, and you have 3 × 47 µF capacitors as peripheral, the suggested decoupling capacitors on your board is 3/2 = (round it to 2) × 47 µF.
Ensure that the recommended voltage regulator current in the board design must be larger than the total current for the merged power rails. Add 30% margin for the voltage regulator current to ensure good reliability and thermal performance.