AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines

ID 683393
Date 9/29/2023
Document Table of Contents

2.2. Rail Merger Requirements

IP voltage rails of same nominal values within the same sequencing group can be merged assuming that the power delivery network to each package balls for each IP is designed with care to meet the tolerance specifications of that IP. Therefore, proper analysis and/or simulations should be done to ensure voltage drop and cross regulations are under control.

As many power rails are merged on the motherboard, the requirement for an LC filter is necessary to ensure systems functionality especially for rail connections to sensitive circuits such as the phase-locked loop (PLL) and clock. Intel® recommends you to follow the LC filter requirements.

For more information about the rail merger requirements, refer to the Intel Agilex® 7 Device Family Pin Connection Guidelines.