1. Agilex™ 7 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused Tiles
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Agilex™ 7 Device Family PDN Design Summary
9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines
2.1.2.1. Recommended Power Tree for the Agilex™ 7 Devices with only P-Tile and E-Tile in the Device Packages
2.1.2.2. Recommended Power Tree for the Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.1.2.3. Recommended Power Tree for the Agilex™ 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.4.1. Agilex™ 7 FPGA Packages Board-Level Decoupling Capacitors Summary
2.4.2. Agilex™ 7 E-Tile Decoupling Capacitors Summary per Tile Agilex™ 7 E-Tile Board-Level Decoupling Capacitors Summary
2.4.3. Agilex™ 7 P-Tile Board-Level Decoupling Capacitors Summary
2.4.4. Agilex™ 7 F-Tile Board-Level Decoupling Capacitors Summary
2.4.5. Agilex™ 7 R-Tile Board-Level Decoupling Capacitors Summary
3.5. VCC Core Board Current Slew Rate
The VCC core fabric has a very high current slew rate. But some of that is filtered out by the metal-insulator-metal (MIM) capacitors as they provide the lowest impedance to the load because of their proximity. With addition of OPDs, most of the remaining fast edges are filtered out, leaving the board cavity capacitors and voltage regulator capacitors to handle only a fraction of the die level current.
You must ensure the PDN can deliver the current specified at the package balls. The Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails section describes the recommended PCB system-level simulation to ensure the voltage tolerance or specification at package balls are met through the design.