AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines

ID 683393
Date 12/04/2023
Public
Document Table of Contents

2.4.3. Intel Agilex® 7 P-Tile Board-Level Decoupling Capacitors Summary

Table 14.   Intel Agilex® 7 P-Tile Decoupling Capacitors Summary per Tile
Intel Agilex® 7 PTC Rail Name Bottom-side Capacitors FPGA Periphery Capacitors Notes
Thick PCB (≥65 mil thickness) Thin PCB (≤65 mil thickness) Thick PCB (≥65 mil thickness) Thin PCB (≤65 mil thickness)
VCC_HSSI_GXP 1x 10uF 0402 1x 10uF 0402 N/A N/A Per each P-Tile
VCCFUSE_GXP 1x 1uF 0201 1x 1uF 0201 N/A N/A

Per each P-Tile.

For the multiple P-Tiles in the device package, use 1x 0402 4.7uF per 2 P-Tiles.

VCCRT_GXP 6x 4.7uF 0201 6x 4.7uF 0201 LC filter capacitors LC filter capacitors

Per each P-Tile.

This is applicable to both reasonable worst case and low power scenario case. For the low power scenario case, the maximum current is 1.5 A, and the difference is the LC filter capacitors.

For more information, refer to Figure 20 and Figure 21.

VCCH_GXP 1x 1uF 0201 1x 1uF 0201 LC filter capacitors LC filter capacitors

Per each P-Tile.

This is applicable to both reasonable worst case and low power scenario case. For the low power scenario case, the maximum current is 0.7 A, and the difference is the LC filter capacitors.

For more information, refer to Figure 18 and Figure 19.

VCCCLK_GXP 1x 1uF 0201 1x 1uF 0201 LC filter capacitors LC filter capacitors Per each P-Tile

Although it is not required to use the recommended decoupling capacitors and LC filters for unused P-Tile, Intel® recommends you to use at least one of each suggested decoupling capacitors for the bottom-side capacitors if the P-Tile is not used.