AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines

ID 683393
Date 9/29/2023
Document Table of Contents

7. Board Power Delivery Network Simulations

In this section, the PDN post-layout simulation is shown in Figure 28 for any Intel Agilex® 7 device family board design and system-level PDN simulation.

Figure 28. Methodology for Device PDN and Transient Noise AnalysisStep load at the package pin is injected to the PCB model to meet voltage droop (DC + AC) at the package pin.

Intel® recommends you to follow the above-mentioned guidelines to design all power rails on the PCB with the recommended decoupling capacitors, voltage regulators, and LC filtering. In the post-layout phase, it is recommended to do the IR drop and transient (time domain) PDN analysis for PCB only. This means, unconventionally, we do not recommend impedance target and frequency target analysis (frequency domain simulation) for the Intel Agilex® 7 device.

To ensure the PDN design performance is within the required tolerance or specification in Table 10, time domain post-layout PDN simulation for some critical power nets such as VCC core, VCCP, VCCPT, VCCIO_PIO, VCCH, and power rails for E-Tile, P-Tile, F-Tile, and R-Tile must be performed.

PDN time domain simulation is only performed on PCB from voltage regulator to package ball. Therefore, package, OPDs, and on-chip models are not required for the PDN time domain simulation.

The following steps show the time domain PDN simulation (as shown in Figure 29):

  1. Obtain the implemented VRM SPICE model for the target power rail.
  2. Extract post-layout PCB model (HSPICE or scattering parameters by using tools such as PowerSI) of the PCB with decoupling capacitors and LC filtering from the voltage regulator (including VRM recommended bulk decoupling capacitors by vendor) to package pin (if use of scattering parameters, the PCB model shall be extracted from DC up to 1GHz). Intel recommends you to convert scattering parameters to circuit model by use of any broadband Spice or IDEM tool to avoid problematic simulation. To avoid simulation divergence, you shall include the small to medium decoupling capacitors on PCB extraction and define ports for the large and bulk capacitors on the PCB when extracting its model. Then, you add the large/bulk capacitors (in the format of spice models) externally in the schematic (as explained in step 3).
  3. Build a schematic in any possible EDA tool (Keysight ADS or Cadence or LTspice or Simplix) with the voltage regulator model (possible HSPICE model) and PCB model extracted from previous step.
    • This schematic represents the voltage regulator plus the PCB or decoupling capacitors model up to package pins.
    • Package, OPDs, or die model are not built into this schematic (Step load at package pin covers frequencies for only PCB, which means high frequency current components are eliminated through package and on-die).
    • Connect the sense pins from the package pin feedback to the voltage regulator sense pins.
  4. Connect the maximum step load current at the package pins shown in Table 11 (for example, for for Intel Agilex® 7 AGF014 core, 200A/µs slew rate and step load of 17A).
  5. Probe voltage drop at the package pin to see if the power rail specification in Table 10 is met (for example, for VCC core, the DC+AC voltage tolerance is ±3%).
    • If not meeting the package power rail tolerance or specification in Table 10, you must check the PCB and adjust the decoupling capacitors or locations.
Figure 29. Time Domain PDN Test Bench Example for Intel Agilex® 7 AGF014 VCC Core"A" is the VCC node at the package ball (all VCC pins at the package are connected to A). Voltage at "A" must be evaluated based on the voltage tolerance.

You must notice that Figure 29 shows a simplified schematic for the PDN transient simulation. In order to avoid non-convergence condition in TD simulation, Intel® recommends you to only include small decoupling capacitors in the PCB model extraction and define ports for large/bulk decoupling capacitors at PCB level and add them to the schematic in Figure 29 manually.

Some of the PCB power rails in the recommended power tree in Figure 1 and Figure 2 is built by merging various power rails (with or without filter). You must define ports in the PCB modeling for each power rail to be able to inject the respective step load for that power rail in the PDN simulation schematic.

The recommended step load along with the static current (obtained from PTC) in a format of a pulse for each power rail is added to power rail ports in the PDN simulation schematic (e.g. Figure 29) and the voltage droop and overshoot are measured against the specification listed in Table 10.

The PDN IR drop analysis is a DC simulation and must be performed on all power rails on the PCB up to package pins to meet the electrical specifications listed in the Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series .

Figure 30 shows the reference stackup used in the PDN design guideline and FPGA decoupling capacitors extraction. However, the FPGA PDN performance is also validated with a thicker PCB such the DK-SI-AGF014E3ES board designed in-house.

Figure 30. Reference Stackup