2.4.5. Intel Agilex® 7 R-Tile Board-Level Decoupling Capacitors Summary
|Intel Agilex® 7 PTC Rail Name||Bottom-side Capacitors||FPGA Periphery Capacitors||Notes|
|Thick PCB (≥65 mil thickness)||Thin PCB (≤65 mil thickness)||Thick PCB (≥65 mil thickness)||Thin PCB (≤65 mil thickness)|
|VCC_HSSI_GXR||2x 10uF 0402||2x 47uF 0805||Per each R-Tile|
|VCCE_PLL_GXR||1x 4.7uF 0201||N/A||Per each R-Tile|
|VCCRT_GXR||4x 10uF 0402||2x 47uF 0805||
Per each R-Tile.
|4x 10uF 0402||2x 220uF 1206 + 3x 100uF 0805||Per each R-Tile: If LDO voltage regulator is used for this power rail.|
|VCCH_GXR||1x 10uF 0402||1x 47uF 0805||
Per each R-Tile.
|VCCED_GXR||1x 10uF 0402||1x 47uF 0805||Per each R-Tile|
|VCCCLK_GXR||2x 10uF 0402||N/A||Per each R-Tile|
|VCCHFUSE_GXR||2x 10uF 0402||N/A||Per each R-Tile|
The capacitors listed in the tables above have been validated on the Intel® development kits and should be used as a reference only. You have the option to choose other capacitors according to specific applications, package size used, temperature range, form factor, and rated voltage, as long as the specifications stated above are met and the LC filter works well. Intel® recommends you to run the simulation to ensure there is no further changes.
This recommended decoupling capacitors solution has been verified along with the use of the recommended switching voltage regulator or LDO in the example power trees. You can use other switching voltage regulators or LDOs as long as you meet the PCB power rail tolerance specification in Table 10. Intel® recommends performing the PCB time domain simulation by using the step load in Table 11 for critical power rails. Intel® do not support customers' PCB PDN time domain simulation. It is your responsibility to use the data and specifications in this document along with the simulation guidance in the Board Power Delivery Network Simulations chapter to perform the PDN time domain simulation.