Agilex™ 7 Power Distribution Network Design Guidelines

ID 683393
Date 7/08/2024
Public
Document Table of Contents

2.3.2. Power Rails Tolerance

This section describes the power rails tolerance and budget (AC tolerance + VR accuracy) on board at package level for the Agilex™ 7 device family. The rail tolerance must be met at the FPGA package ball. You must consider the following instructions to measure the rail tolerance:

  • VCCL (core power net) measurement is taken at the FPGA remote differential sense lines (there is assigned differential sense pins at FPGA package) with the scope set to bandwidth limited at 20 MHz.
  • VCCERT1_FHT_GXF has dedicated differential sense line at package level to compensate the IR drop at die level.
  • Other power rails (except for VCCL (core power)), the rail tolerance must be met at the board vias on the bottom layer directly connected to the package power balls.
  • For all other power rails with the objective to compensate the IR drop on those specific power rails, place their respective voltage regulator sense point within the FPGA pin field, connecting to one of the rail's BGA pins which represents the worst IR drop on the path.
Table 10.   Agilex™ 7 AGF Devices with only E-Tile and P-Tile PCB Power Rail Tolerance
Power Tree Rail Name Vnom (Required) (V) Recommended VR Accuracy (% of Vnom) Recommended VR Ripple (% of Vnom) Recommended AC Transient (% of Vnom) Maximum AC Tolerance + VR Accuracy (% of Vnom) 2
VCCL:
  • VCC/VCCP
  • VCCL_HPS
  • VCCPLLDIG_HPS
VID (0.68, 0.8, 0.85) ±0.5% ±2.5% ±3%
P0V8_GR1:
  • VCCL_SDM
  • VCCPLLDIG_SDM
0.8 ±0.5% ±2.5% ±3%
VCCH:
  • VCCH
  • VCCH_SDM
  • VCCFUSE_GXP
  • VCC_HSSI_GXP
  • VCC_HSSI_GXE
  • VCCRTPLL_GXE
  • VCCRT_GXE
  • VCCRT_GXP
0.9 ±0.5% ±2.5% ±3%
P1V8_GR2 3:
  • VCCPT
  • VCCADC
  • VCCPLL_SDM
  • VCCPLL_HPS
1.8 ±0.5% ±1% 4 ±3.5% ±5%
P1V8_GR23:
  • VCCCLK_GXP
  • VCCH_GXP
1.8 ±0.5% ±0.5% ±2% ±3%
VCCH_GXE 1.1 ±0.5% ±0.5% ±2% ±3%
VCCCLK_GXE 2.5 ±0.5% ±0.5% ±3.5% ±5%
P1V2_GR3:
  • VCCIO_PIO
  • VCCIO_PIO_SDM
  • VCCRCORE
  • VCCA_PLL
1.2 ±0.5% ±1%4 ±3.5% ±5%
P1V8_GR3:
  • VCCIO_SDM
  • VCCIO_HPS
  • VCCFUSE_SDM
1.8 ±0.5% ±1%4 ±3.5% ±5%
Table 11.   Agilex™ 7 AGF and AGI Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance
Power Tree Rail Name Vnom (Required) (V) Recommended VR Accuracy (% of Vnom) Recommended VR Ripple (% of Vnom) Recommended AC Transient (% of Vnom) Maximum AC Tolerance + VR Accuracy (% of Vnom)2
VCCL:
  • VCC/VCCP
  • VCCL_HPS
  • VCCPLLDIG_HPS
VID (0.68, 0.8, 0.85) ±0.5% ±2.5% ±3%
P0V8_GR1:
  • VCC_HSSI_GXF
  • VCCL_SDM
  • VCCPLLDIG_SDM
  • VCCH
  • VCCH_SDM
0.8 ±0.5% ±2.5% ±3%
P0V9_GR1:
  • VCC_HSSI_GXR
  • VCCH_SDM
0.9 ±0.5% ±2.5% ±3%
VCCE_PLL_GXR 1.0 ±0.5% ±2.0% ±2.5%
P1V0_GR13:
  • VCCERT_FGT_GXF
  • VCCERT1_FHT_GXF
  • VCCERT2_FHT_GXF
  • VCCRT_GXR
5 6
1.0 ±0.5% ±2.0% ±2.5%
P1V0_GR23:
  • VCCFUSECORE_GXF/ VCCFUSEWR_GXF
  • VCCCLK_GXR
1.0 ±0.5% ±2.5% ±3%
P1V0_GR23:
  • VCCHFUSE_GXR
1.0 ±0.5% ±1%4 ±3.5% ±5%
VCCED_GXR 0.9 ±0.5% ±2.5% ±3%
VCCEHT_FHT_GXF 1.5 ±0.5% ±2.0% ±2.5%
P1V8_GR23:
  • VCCPT
  • VCCADC
  • VCCPLL_SDM
  • VCCPLL_HPS
1.8 ±0.5% ±1%4 ±3.5% ±5%
P1V8_GR23:
  • VCCH_GXR
  • VCCH_FGT_GXF 7
1.8 ±0.5% ±2.0% ±2.5%
P1V8_GR23:
  • VCCCLK_GXF
1.8 ±0.5% ±2.5% ±3%
P1V2_GR3:
  • VCCIO_PIO
  • VCCIO_PIO_SDM
  • VCCRCORE
  • VCCA_PLL
1.2 ±0.5% ±1%4 ±3.5% ±5%
P1V8_GR3:
  • VCCIO_SDM
  • VCCIO_HPS
  • VCCFUSEWR_SDM
1.8 ±0.5% ±1%4 ±3.5% ±5%
Table 12.   Agilex™ 7 AGM Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance
Power Tree Rail Name Vnom (Required) (V) Recommended VR Accuracy (% of Vnom) Recommended VR Ripple (% of Vnom) Recommended AC Transient (% of Vnom) Maximum AC Tolerance + VR Accuracy (% of Vnom)2
VCCL:
  • VCC/VCCP
  • VCCL_HPS
  • VCCPLLDIG_HPS
VID (0.68, 0.8, 0.85) ±0.5% ±2.5% ±3%
P0V8_GR1:
  • VCC_HSSI_GXF
  • VCCL_SDM
  • VCCPLLDIG_SDM
  • VCCH
  • VCCH_SDM
  • VCCLPLL_NOC
  • VCCPLLDIG_NOC
0.8 ±0.5% ±2.5% ±3%
P0V9_GR1:
  • VCC_HSSI_GXR
  • VCCH_SDM
  • VCCED_GXR
0.9 ±0.5% ±2.5% ±3%
VCCE_PLL_GXR 1.0 ±0.5% ±2.0% ±2.5%
P1V0_GR13:
  • VCCERT_FGT_GXF
  • VCCERT1_FHT_GXF
  • VCCERT2_FHT_GXF
  • VCCRT_GXR
5 6
1.0 ±0.5% ±2.0% ±2.5%
P1V0_GR13:
  • VCCFUSECORE_GXF 7/ VCCFUSEWR_GXF
  • VCCCLK_GXR
1.0 ±0.5% ±2.5% ±3%
P1V0_GR13:
  • VCCHFUSE_GXR
1.0 ±0.5% ±1%4 ±3.5% ±5%
VCCEHT_FHT_GXF 1.5 ±0.5% ±2.0% ±2.5%
P1V8_GR3a3:
  • VCCPT
  • VCCADC
  • VCCPLL_SDM
  • VCCPLL_HPS
  • VCCIO_SDM
  • VCCIO_HPS
  • VCCFUSEWR_SDM
1.8 ±0.5% ±1%4 ±3.5% ±5%
P1V8_GR3a3:
  • VCCH_GXR
  • VCCH_FGT_GXF7
1.8 ±0.5% ±2.0% ±2.5%
P1V8_GR3a3:
  • VCCCLK_GXF
1.8 ±0.5% ±2.5% ±3%
P1V8_GR3a3:
  • VCCPLL_NOC
  • VCCIO_NOC
1.8 ±0.5% ±0.5% ±2.0% ±3%
VCCM_PUMP_HBM 2.5 ±0.5% ±1%4 ±3.5% ±5%
P1V2_GR3b:
  • VCCIO_PIO
  • VCCIO_PIO_SDM
  • VCCRCORE
  • VCCIO_UIB
1.2 ±0.5% ±1%4 ±3.5% ±5%

The actual specification for each power rail at package level is listed in the Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series . To reduce the PCB cost, some power rails are merged by using only a single voltage regulator to feed the power rails. The AC + DC specification in this design guideline is based on this design. However, you have the option to not combine the power rails on the PCB in your design.

You can combine the analog power rails on the PCB (provided that the nominal voltages are the same) by using a single voltage regulator on the PCB to feed the power rails to achieve the minimum cost. If you implement this design, you must ensure the power rail specifications of the combined power rails on the PCB and voltage regulator must follow the most stringent specification of those package power rails.

The analog power rails can also be merged with the digital power rails if they are the same voltage and are in the same power-up or power-down sequence. However, ensure using the noise isolation filter from the digital power rails to analog power rails (since they are more sensitive to noise).

2 The specification stands for VR accuracy + (VR ripple + AC transient) rail tolerance and must be measured and met at package pin/ball.
3 These power rails have different tolerances, when merged in one VR, use the tight tolerance requirement in board design.
4 If you select a voltage regulator with lower than 1% voltage regulator ripple specification, the extra margin is added to the recommended AC transient specification.
5 The P1V0_GR1 specification for these individual specific power rails are ±2.5% (AC tolerance + VR accuracy) at package pin.This specification is also up to 1 MHz. The voltage regulator ripple specification is 5 mV p-p maximum. The AC noise specification above 1 MHz at package pin is ±15 mV (30 mV p-p). This can be measured by a high pass filter probe above 1 MHz.
6 The VCCERT_FGT_GXF, VCCERT1_FHT_GXF, VCCERT2_FHT_GXF, and VCCRT_GXR can be merged to P1V0_GR1. The final specification of the merged power rail is the most stringent among those power rails.
7 The VCCH_FGT_GXF specification for this individual power rail per Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series is ±2.5% (VR accuracy + AC tolerance). This applies up to 1 MHz (use of probe with low pass filter at 1 MHz at package pin, the voltage regulator ripple specification is 5 mV p-p maximum). The AC noise specification above 1 MHz at package pin is ±15 mV (30 mV p-p). This can be measured by a high pass filter probe above 1 MHz.