4.1. P-Tile Rail LC Filter Board Scheme and Connection
The filtering topology in Figure 17, Figure 18, and Figure 20 are recommended for the P-Tile voltage rails (VCCCLK_GXP, VCCH_GXP, VCCRT_GXP) in the Power Tree for noise filtering purpose. The filter can be placed as close to FPGA as periphery capacitors in the recommended decoupling capacitors table in the Decoupling Capacitors Recommendation. In addition to the LC filter, you must also add the bottom or backside capacitors recommended in the decoupling capacitors table in the Decoupling Capacitors Recommendation within pin or via field on the bottom layer. Implement one set of LC filters for each tile on the FPGA.