AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines

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ID 683393
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 Power Distribution Network Design Guidelines Overview 2. Power Delivery Overview 3. Board Power Delivery Network Recommendations 4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 5. PCB PDN Design Guideline for Unused Tiles 6. PCB Voltage Regulator Recommendation for PCB Power Rails 7. Board Power Delivery Network Simulations 8. Intel Agilex® 7 Device Family PDN Design Summary 9. Document Revision History for AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines
1. Intel Agilex® 7 Power Distribution Network Design Guidelines Overview x
1.1. Device Guidelines Status for Intel Agilex® 7 Devices
2. Power Delivery Overview x
2.1. Power Architecture 2.2. Rail Merger Requirements 2.3. Power Rails Specification 2.4. Decoupling Capacitors Recommendation
2.1. Power Architecture x
2.1.1. Power Budget 2.1.2. Power Tree
2.1.2. Power Tree x
2.1.2.1. Recommended Power Tree for the Intel Agilex® 7 Devices with only P-Tile and E-Tile in the Device Packages 2.1.2.2. Recommended Power Tree for the Intel Agilex® 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages 2.1.2.3. Recommended Power Tree for the Intel Agilex® 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.3. Power Rails Specification x
2.3.1. Power Nets 2.3.2. Power Rails Tolerance 2.3.3. Power Nets and Transient Specifications
2.3.1. Power Nets x
2.3.1.1. Intel Agilex® 7 Package Power Nets and Subsystems Details
2.4. Decoupling Capacitors Recommendation x
2.4.1. Intel Agilex® 7 FPGA Packages Board-Level Decoupling Capacitors Summary 2.4.2. Intel Agilex® 7 E-Tile Board-Level Decoupling Capacitors Summary 2.4.3. Intel Agilex® 7 P-Tile Board-Level Decoupling Capacitors Summary 2.4.4. Intel Agilex® 7 F-Tile Board-Level Decoupling Capacitors Summary 2.4.5. Intel Agilex® 7 R-Tile Board-Level Decoupling Capacitors Summary
3. Board Power Delivery Network Recommendations x
3.1. Board Decoupling Capacitors and Power Flooding Guides 3.2. FPGA Core Fabric VCC Voltage Regulator Selection 3.3. Remote Sense Connections 3.4. Load Line Requirements 3.5. VCC Core Board Current Slew Rate
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
4.1. P-Tile Rail LC Filter Board Scheme and Connection 4.2. E-Tile Rail LC Filter Board Scheme and Connection 4.3. F-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator 4.4. R-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
5. PCB PDN Design Guideline for Unused Tiles x
5.1. PDN Design Guideline for Unused E-Tile 5.2. PDN Design Guideline for Unused P-Tile 5.3. PDN Design Guideline for Unused R-Tile 5.4. PDN Design Guideline for Unused F-Tile
1. Intel Agilex® 7 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused Tiles
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Intel Agilex® 7 Device Family PDN Design Summary
9. Document Revision History for AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines

8. Intel Agilex® 7 Device Family PDN Design Summary

The summary of the Intel Agilex® 7 device family PDN design guidelines are as follow:

  1. Current PDN design guidelines stand for the maximum power consumption—the worst use case.
    • If for any reason (various applications, configurations, or the PTC) power data is lower than the maximum power used for the PDN design guideline, you must scale the recommended decoupling capacitors based on the ratio of design current to the maximum current. Use of ratio is an estimate and time domain simulation are mandatory to ensure meeting package ball voltage specification.
  2. Apply the recommended power-up or power-down sequence grouping on the PCB. For more information, refer to AN 692: Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel Agilex® 7 Devices and Intel Agilex® 7 Power Management User Guide.
  3. Use the recommended power tree presented in the Power Tree for each Intel Agilex® 7 device with the suggested merged power nets.
    • For example, minimum 9 x voltage regulator is required on the PCB for the Intel Agilex® 7 AGF014 2486A Package Early Silicon and minimum 10 x voltage regulator is required on the PCB for Intel Agilex® 7 AGF014 production silicon. The recommended voltage regulators are only for FPGA and do not cover other devices on the board.
    • The minimum recommended number of voltage regulators on PCB is due to cost, area, and power-effective solution strategies. However, you can separate all power rails by the use of separate voltage regulators.
  4. Use the recommended voltage regulators in the power tree or design your own voltage regulator based on the required maximum ripple or total current support per power rail on the PCB-VRM inductors or bulk capacitors must be designed separately. Tables in the Decoupling Capacitors Recommendation show the FPGA decoupling capacitors and do not include the voltage regulator bulk capacitors.
  5. Use the recommended bottom-side or FPGA periphery decoupling capacitors for each power net.
  6. Use the recommended LC filters for power nets.
  7. Use of sense line for IR drop compensation.
  8. Configure the FPGA to follow the maximum recommended step load allowed at the package pin.
  9. Do post-layout simulation for the IR drop analysis to see if this is within the DC specification at the package pin in Table 10.
  10. Do post-layout time domain PCB simulation up to the package pin for critical power nets such as the VCC core to meet the AC voltage tolerance or specification at the package pin in Table 10.
  11. If not meeting the voltage tolerance (DC or AC) at the FPGA package pin, you must check the PCB and update the decoupling capacitors and redo the simulations.
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