AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines

ID 683393
Date 9/29/2023
Document Table of Contents

8. Intel Agilex® 7 Device Family PDN Design Summary

The summary of the Intel Agilex® 7 device family PDN design guidelines are as follow:

  1. Current PDN design guidelines stand for the maximum power consumption—the worst use case.
    • If for any reason (various applications, configurations, or the PTC) power data is lower than the maximum power used for the PDN design guideline, you must scale the recommended decoupling capacitors based on the ratio of design current to the maximum current. Use of ratio is an estimate and time domain simulation are mandatory to ensure meeting package ball voltage specification.
  2. Apply the recommended power-up or power-down sequence grouping on the PCB. For more information, refer to AN 692: Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel Agilex® 7 Devices and Intel Agilex® 7 Power Management User Guide.
  3. Use the recommended power tree presented in the Power Tree for each Intel Agilex® 7 device with the suggested merged power nets.
    • For example, minimum 9 x voltage regulator is required on the PCB for the Intel Agilex® 7 AGF014 2486A Package Early Silicon and minimum 10 x voltage regulator is required on the PCB for Intel Agilex® 7 AGF014 production silicon. The recommended voltage regulators are only for FPGA and do not cover other devices on the board.
    • The minimum recommended number of voltage regulators on PCB is due to cost, area, and power-effective solution strategies. However, you can separate all power rails by the use of separate voltage regulators.
  4. Use the recommended voltage regulators in the power tree or design your own voltage regulator based on the required maximum ripple or total current support per power rail on the PCB-VRM inductors or bulk capacitors must be designed separately. Tables in the Decoupling Capacitors Recommendation show the FPGA decoupling capacitors and do not include the voltage regulator bulk capacitors.
  5. Use the recommended bottom-side or FPGA periphery decoupling capacitors for each power net.
  6. Use the recommended LC filters for power nets.
  7. Use of sense line for IR drop compensation.
  8. Configure the FPGA to follow the maximum recommended step load allowed at the package pin.
  9. Do post-layout simulation for the IR drop analysis to see if this is within the DC specification at the package pin in Table 10.
  10. Do post-layout time domain PCB simulation up to the package pin for critical power nets such as the VCC core to meet the AC voltage tolerance or specification at the package pin in Table 10.
  11. If not meeting the voltage tolerance (DC or AC) at the FPGA package pin, you must check the PCB and update the decoupling capacitors and redo the simulations.