AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines

ID 683393
Date 12/04/2023
Document Table of Contents

4.4. R-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator

The R-Tile requires a strict connection requirement to eliminate the need for power-down sequencing (PDS) control circuits. Using the board connections shown below, the R-Tile removes the PDS requirement (such as the PDS requirement in the Intel® Stratix® 10 device family)—no pull-down discharge FETs or resistors on voltage rails is required. Therefore, the Intel Agilex® 7 device is a PDS-free FPGA, except for E-Tile.

For the VCCRT_GXR rail that is designed with the recommended LTC7151S voltage regulator (500 KHZ switching frequency is recommended), with a very tight noise specification, you do not need to add filter to this power rail (refer to the recommended power tree). However, if noisy switching voltage regulator is used, an elaborate filter design is required to dampen the noise in the power rail. Perform the PDN transient simulation to validate this power rail design against the specifications.

If you are using the LDO voltage regulator to meet the tight noise specification for this power rail, the recommended LDO is 2x ADP1765 and it is not needed to add LC filter when using LDO.

The maximum voltage regulator (VR) voltage ripple allowed for the VCCRT_GXR is 5mV and for VCCH_GXR is 7mV. If you do not meet this VR ripple specification for the R-Tile power rails by selecting a noisy VR, Intel® recommends using the recommended LC filters to block the noise.

Figure 27. Connection Requirement and Filter Recommendation for VCCH_GXR per TileUnder the condition of using noisy switching voltage regulator.