AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines

ID 683393
Date 9/29/2023
Document Table of Contents

2.4. Decoupling Capacitors Recommendation

Solid and recommended FPGA decoupling capacitors requirement on board-level PCB are listed in this section in the table format for all power nets and based on the maximum FPGA power consumption and the recommended power trees. The table does not include recommended decoupling/bulk capacitors at voltage regulators. You must select the voltage regulator capacitors (bulk decoupling capacitors) based on the data sheet specification from the voltage regulator supplier and required specifications by Intel® such as the maximum voltage regulator ripple and maximum total current support for that specific power rail or combined power rails. You must perform the PDN transient simulation if your design is not following the recommendation.

You must follow the recommended decoupling capacitors along with the power rail grouping and recommended voltage regulator on the PCB to ensure your are meeting the power rail tolerance and specification at package ball. For boards/PCBs that consume less power than the maximum power consumption, you must scale the decoupling capacitors by ratio of the board power consumption to the maximum power consumption per power rail. However, transient PDN simulation must be performed to ensure meeting the power rail tolerance at package ball.