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2.4. Decoupling Capacitors Recommendation
The recommended decoupling capacitors for FPGA on board-level PCBs are listed in this section in table format for all power nets, based on the maximum power consumption of the FPGA and suggested power tree configurations. You must select the voltage regulator capacitors (bulk decoupling capacitors) based on the data sheet specification from the voltage regulator supplier and required specifications by Altera such as the maximum voltage regulator ripple and maximum total current support for that specific power rail or combined power rails. You must perform the PDN transient simulation if your design is not following the recommendation.
Follow the recommended decoupling capacitors, power rail grouping, and recommended voltage regulator on the PCB to meet power rail tolerance and specifications at the package ball. For boards that use less power than the maximum, scale the decoupling capacitors by the radio of board's power consumption to the maximum power per power rail. However, you must perform transient PDN simulations to verify power rail tolerance at the package ball.
Section Content
Agilex 7 FPGA Packages Board-Level Decoupling Capacitors Summary
Agilex 7 E-Tile Decoupling Capacitors Summary per Tile Agilex 7 E-Tile Board-Level Decoupling Capacitors Summary
Agilex 7 P-Tile Board-Level Decoupling Capacitors Summary
Agilex 7 F-Tile Board-Level Decoupling Capacitors Summary
Agilex 7 R-Tile Board-Level Decoupling Capacitors Summary