AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines

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ID 683393
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 Power Distribution Network Design Guidelines Overview 2. Power Delivery Overview 3. Board Power Delivery Network Recommendations 4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 5. PCB PDN Design Guideline for Unused Tiles 6. PCB Voltage Regulator Recommendation for PCB Power Rails 7. Board Power Delivery Network Simulations 8. Intel Agilex® 7 Device Family PDN Design Summary 9. Document Revision History for AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines
1. Intel Agilex® 7 Power Distribution Network Design Guidelines Overview x
1.1. Device Guidelines Status for Intel Agilex® 7 Devices
2. Power Delivery Overview x
2.1. Power Architecture 2.2. Rail Merger Requirements 2.3. Power Rails Specification 2.4. Decoupling Capacitors Recommendation
2.1. Power Architecture x
2.1.1. Power Budget 2.1.2. Power Tree
2.1.2. Power Tree x
2.1.2.1. Recommended Power Tree for the Intel Agilex® 7 Devices with only P-Tile and E-Tile in the Device Packages 2.1.2.2. Recommended Power Tree for the Intel Agilex® 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages 2.1.2.3. Recommended Power Tree for the Intel Agilex® 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.3. Power Rails Specification x
2.3.1. Power Nets 2.3.2. Power Rails Tolerance 2.3.3. Power Nets and Transient Specifications
2.3.1. Power Nets x
2.3.1.1. Intel Agilex® 7 Package Power Nets and Subsystems Details
2.4. Decoupling Capacitors Recommendation x
2.4.1. Intel Agilex® 7 FPGA Packages Board-Level Decoupling Capacitors Summary 2.4.2. Intel Agilex® 7 E-Tile Board-Level Decoupling Capacitors Summary 2.4.3. Intel Agilex® 7 P-Tile Board-Level Decoupling Capacitors Summary 2.4.4. Intel Agilex® 7 F-Tile Board-Level Decoupling Capacitors Summary 2.4.5. Intel Agilex® 7 R-Tile Board-Level Decoupling Capacitors Summary
3. Board Power Delivery Network Recommendations x
3.1. Board Decoupling Capacitors and Power Flooding Guides 3.2. FPGA Core Fabric VCC Voltage Regulator Selection 3.3. Remote Sense Connections 3.4. Load Line Requirements 3.5. VCC Core Board Current Slew Rate
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
4.1. P-Tile Rail LC Filter Board Scheme and Connection 4.2. E-Tile Rail LC Filter Board Scheme and Connection 4.3. F-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator 4.4. R-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
5. PCB PDN Design Guideline for Unused Tiles x
5.1. PDN Design Guideline for Unused E-Tile 5.2. PDN Design Guideline for Unused P-Tile 5.3. PDN Design Guideline for Unused R-Tile 5.4. PDN Design Guideline for Unused F-Tile
1. Intel Agilex® 7 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused Tiles
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Intel Agilex® 7 Device Family PDN Design Summary
9. Document Revision History for AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines

3.2. FPGA Core Fabric VCC Voltage Regulator Selection

Intel® recommends you to use the industry standard common footprints for power stages. This provides you the flexibility to choose between different vendors during the validation phases. This also allows you to choose the vendor that best fit your PCB performance and cost targets without impacting the program schedule. The vendors that offer power stages for core in the industry standard common footprints are:

  • MPS
  • Infineon
  • Fairchild
  • TI
  • Intersil
  • ADI

The following controllers have been validated for operation and communication with the Intel Agilex® 7 Power Management Controller Tool and added to the existing list of supported controllers and power stages.

The recommended VCC core voltage regulators in Table 17 are available in the Intel® Quartus® Prime software for your selection. Intel® has already qualified these voltage regulators for the VID application. The PMBus communication is already validated by Intel® .

Table 17.  List of Supported Controllers and Power Stages
Vendor Controller Power Stage Number of Phase
MPS MPS2975/2972 MP86956A (60A) 5
Intersil/Renesas ISL68236 ISL99227 (60A) 5
ADI LTC3888-1 LTC7051 (60A) 4

Validated VR controllers from the Intel® Stratix® 10 device are still supported too. For more details, refer to the Intel® Stratix® 10 Power Management User Guide.

The following power design is being tested on internal boards (development kits). Hence, Intel® recommends you to follow this VCC core voltage regulator diagram as a reference.

Figure 7. VCC/VCCP Core Voltage Regulator Design Implemented on the Intel Agilex® 7 AGF014 2486A FPGA Development Kits
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