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1. Intel Agilex® 7 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused Tiles
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Intel Agilex® 7 Device Family PDN Design Summary
9. Document Revision History for AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines
2.1.2.1. Recommended Power Tree for the Intel Agilex® 7 Devices with only P-Tile and E-Tile in the Device Packages
2.1.2.2. Recommended Power Tree for the Intel Agilex® 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.1.2.3. Recommended Power Tree for the Intel Agilex® 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.4.1. Intel Agilex® 7 FPGA Packages Board-Level Decoupling Capacitors Summary
2.4.2. Intel Agilex® 7 E-Tile Board-Level Decoupling Capacitors Summary
2.4.3. Intel Agilex® 7 P-Tile Board-Level Decoupling Capacitors Summary
2.4.4. Intel Agilex® 7 F-Tile Board-Level Decoupling Capacitors Summary
2.4.5. Intel Agilex® 7 R-Tile Board-Level Decoupling Capacitors Summary
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4.2. E-Tile Rail LC Filter Board Scheme and Connection
The E-Tile has a strict connection requirement to eliminate the need for power-down sequencing (PDS) control circuits. With the connections in Figure 22 and Figure 24, the E-Tile eliminates the PDS requirement existing in the Intel® Stratix® 10 device family—no pull-down discharge FETs or resistors on voltage rails are required. The filter can be placed as close to FPGA as periphery capacitors in Table 12. Implement one set of LC filters for each tile on the FPGA.
Figure 22. Connection Requirement and Filter Recommendation for VCCRT_GXE per Tile
Figure 23. Connection Requirement and Filter Recommendation for VCCRT_GXE per Tile (Low Power Scenario)
Figure 24. Connection Requirement and Filter Recommendation for VCCRTPLL_GXE per Tile