AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines

ID 683393
Date 12/04/2023
Public
Document Table of Contents

4.2. E-Tile Rail LC Filter Board Scheme and Connection

The E-Tile has a strict connection requirement to eliminate the need for power-down sequencing (PDS) control circuits. With the connections in Figure 22 and Figure 24, the E-Tile eliminates the PDS requirement existing in the Intel® Stratix® 10 device family—no pull-down discharge FETs or resistors on voltage rails are required. The filter can be placed as close to FPGA as periphery capacitors in Table 12. Implement one set of LC filters for each tile on the FPGA.

Figure 22. Connection Requirement and Filter Recommendation for VCCRT_GXE per Tile
Figure 23. Connection Requirement and Filter Recommendation for VCCRT_GXE per Tile (Low Power Scenario)
Figure 24. Connection Requirement and Filter Recommendation for VCCRTPLL_GXE per Tile