1.3. Synchronized ADC to Intel® Agilex™ Dual Link
The output of the AND gate connects to the j204c_rx_alldev_lane_align and j204c_rx_alldev_emblock_align ports of each IP. Refer to Figure 4 for the required connections. The IPs need to be out of reset simultaneously to complete the link initialization sequence. Multiple IPs are put into the same JESD204C subsystem so that the reset of each IP is released by the same reset sequencer simultaneously.
For subclass 1, the SYSREF pulse is the timing reference of the entire JESD204C subsystem. It is important to phase-align the SYSREF pulses to the FPGA and converters.
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