AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel® Agilex™ FPGA E-Tile JESD204C RX IP

ID 683537
Date 9/21/2020
Document Table of Contents

1.3. Synchronized ADC to Intel® Agilex™ Dual Link

To synchronize multiple RX IPs within the Intel® Agilex™ device, connect the following signals from each IP with an AND gate respectively:
  • j204c_rx_dev_lane_align
  • j204c_rx_dev_emblock_align

The output of the AND gate connects to the j204c_rx_alldev_lane_align and j204c_rx_alldev_emblock_align ports of each IP. Refer to Figure 4 for the required connections. The IPs need to be out of reset simultaneously to complete the link initialization sequence. Multiple IPs are put into the same JESD204C subsystem so that the reset of each IP is released by the same reset sequencer simultaneously.

Table 1.  IP Ports Connection Summary Table summarizes the IP ports connection for each subclass in the dual link for multi-device synchronization.
Subclass j204c_rx_alldev_lane_align j204c_rx_alldev_emblock_align Reset Remark
0 ANDed and re-distribute ANDed and re-distribute Simultaneous Refer to

For subclass 1, the SYSREF pulse is the timing reference of the entire JESD204C subsystem. It is important to phase-align the SYSREF pulses to the FPGA and converters.

Note: For Subclass 0 IPs, connect the j204c_rx_sysref port to ground.
Figure 4. Dual Link Use Case of the Synchronized ADCs and FPGA
Figure 5. Clock and Reset Scheme of the Synchronized Dual Link
Note: To add JESD204C Intel® FPGA IPs for interfacing with more than one ADC, modifications are needed to the Platform Designer system and top-level HDL of the design example.

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