AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA E-Tile JESD204C RX IP
ID
683537
Date
11/30/2024
Public
1.1. ADC to Intel Agilex® 7 Dual Link Design Overview
1.2. ADC to Intel Agilex® 7 Dual Link Design Implementation Guidelines
1.3. Synchronized ADC to Intel Agilex® 7 Dual Link
1.4. Downloading and Operating the Design Example
1.5. Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.1.3. Editing TX Simulation Model Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.1.4. Editing TX Simulation Model Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.1.5. Editing Simulation Testbench for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.1.6. Adding IP Signals to the Simulation Waveform
1.3.1.7. Updating the Simulation Script
1.3.1.8. Simulating the Dual Link Design
1.3.1.9. Viewing the Simulation Results
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.2.4. Compiling the Design in Quartus® Prime Software
1.3. Synchronized ADC to Intel Agilex® 7 Dual Link
To synchronize multiple RX IPs within the Intel Agilex® 7 device, connect the following signals from each IP with an AND gate respectively:
- j204c_rx_dev_lane_align
- j204c_rx_dev_emblock_align
The output of the AND gate connects to the j204c_rx_alldev_lane_align and j204c_rx_alldev_emblock_align ports of each IP. Refer to Figure 4 for the required connections. The IPs need to be out of reset simultaneously to complete the link initialization sequence. Multiple IPs are put into the same JESD204C subsystem so that the reset of each IP is released by the same reset sequencer simultaneously.
| Subclass | j204c_rx_alldev_lane_align | j204c_rx_alldev_emblock_align | Reset | Remark |
|---|---|---|---|---|
| 0 | ANDed and re-distribute | ANDed and re-distribute | Simultaneous | Refer to Figure 4 |
| 1 |
For subclass 1, the SYSREF pulse is the timing reference of the entire JESD204C subsystem. It is important to phase-align the SYSREF pulses to the FPGA and converters.
Note: For Subclass 0 IPs, connect the j204c_rx_sysref port to ground.
Figure 4. Dual Link Use Case of the Synchronized ADCs and FPGA
Figure 5. Clock and Reset Scheme of the Synchronized Dual Link
Note: To add JESD204C Intel® FPGA IPs for interfacing with more than one ADC, modifications are needed to the Platform Designer system and top-level HDL of the design example.