ID
683537
Date
9/21/2020
Public
Visible to Intel only — GUID: gtw1576570814205
Src Path: Ixiasoft
1.1. ADC to Intel® Agilex™ Dual Link Design Overview
1.2. ADC to Intel® Agilex™ Dual Link Design Implementation Guidelines
1.3. Synchronized ADC to Intel® Agilex™ Dual Link
1.4. Downloading and Operating the Design Example
1.5. Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel® Agilex™ FPGA E-Tile JESD204C RX IP
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel® Agilex™ Dual Link
1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel® Agilex™ Dual Link
1.3.1.3. Editing TX Simulation Model Platform Designer System for Synchronized ADC to Intel® Agilex™ Dual Link
1.3.1.4. Editing TX Simulation Model Top-Level HDL for Synchronized ADC to Intel® Agilex™ Dual Link
1.3.1.5. Editing Simulation Testbench for Synchronized ADC to Intel® Agilex™ Dual Link
1.3.1.6. Adding IP Signals to the Simulation Waveform
1.3.1.7. Updating the Simulation Script
1.3.1.8. Simulating the Dual Link Design
1.3.1.9. Viewing the Simulation Results
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel® Agilex™ Dual Link
1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel® Agilex™ Dual Link
1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Intel® Agilex™ Dual Link
1.3.2.4. Compiling the Design in Intel® Quartus® Prime Software
Visible to Intel only — GUID: gtw1576570814205
Src Path: Ixiasoft
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel® Agilex™ FPGA E-Tile JESD204C RX IP
This application note provides guidelines on how to scale up the single link of the JESD204C Intel® FPGA IP design example generated from the Intel® Quartus® Prime software to handle a dual link system. A single link in JESD204C has one or more high speed transceiver lanes or channels.
In some JESD204C applications, multiple analog-to-digital converters (ADCs) are used to sample the analog signals synchronously. Hence, synchronization between multiple converters in the array is required. In these applications, multiple converters interface with a single logic device, such as the Intel® Agilex™ FPGA E-tile.
Before implementing the dual link design, you must generate the receiver (RX) single-link design example from the Intel® Quartus® Prime software. Intel® recommends that you perform an RTL simulation on this single link design example to confirm the functionality matches your expectation before transforming the design example to the dual link design. The guidelines in the following section assume the JESD204C parameters for each link in the dual link design are identical.
Figure 1. JESD204C Dual LinkFigure shows one dual link. All lanes are aligned.
- ADC to Intel Agilex Dual Link Design Overview
- ADC to Intel Agilex Dual Link Design Implementation Guidelines
- Synchronized ADC to Intel Agilex Dual Link
- Downloading and Operating the Design Example
- Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex FPGA E-Tile JESD204C RX IP