1.1. ADC to Intel® Agilex™ Dual Link Design Overview
The design example Platform Designer system and top-level HDL file are designed for easy implementation of a JESD204C dual link use case. In the top-level HDL file, each link in a JESD204C link use case corresponds to an instantiation of a JESD204C Intel® FPGA IP and a pattern checker. The dual link design is created by adding multiple JESD204C Intel® FPGA IPs and pattern checkers to a single link design example. The LINK parameter at the top-level HDL generates multiple pattern checkers. You must duplicate JESD204C Intel® FPGA IPs in the Platform Designer and make connections to the pattern checkers. For a synchronized dual link, AND gates are used to combine the alignment signals.
The j204c_rx_ip subsystem in the design example contains one RX IP to interface with one ADC. To interface with multiple synchronized converters, the j204c_rx_ip should contain multiple IPs.
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