AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel® Agilex™ FPGA E-Tile JESD204C RX IP

ID 683537
Date 9/21/2020
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1.3.1.8. Simulating the Dual Link Design

After modifications to the j204c_rx_ss.qsys, j204c_rx_ip.qsys, intel_j204c_ed_rx.sv, j204c_tx_ss.qsys, j204c_tx_ip.qsys, intel_j204c_ed_tx.sv, tb_top.sv, and <simulator>_files.tcl, you are ready to simulate the dual link design using the simulator of your choice. The following example uses the ModelSim‐ Intel® FPGA Edition.

  1. Launch the ModelSim‐ Intel® FPGA Edition.
  2. From the File menu, select Change Directory.
  3. Select simulation/mentor.
  4. To run the simulation script, type the following command at the transcript prompt:
    do modelsim_sim.tcl
    Note: Depending on your simulator, the simulation may take a few hours to complete. For the Modelsim- Intel® FPGA Edition, the simulation takes 2 to 3 hours.

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