ID 683537
Date 9/21/2020
Public

## 1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel® Agilex™ Dual Link

The generate statement in the Verilog HDL file uses the LINK system parameter as an index variable to generate the requisite number of instances for the dual link use case.
1. Open the top-level HDL file (intel_j204c_ed_rx.sv) in a text editor.
3. Insert the newly exported ports from the j204c_rx_ss Platform Designer system instantiation.
4. To make the connections for the Platform Designer ports:
1. For RX link reset and frame reset, distribute the rx_rst[0] wire from the reset sequencer in Platform Designer to the IPs and pattern checkers of the second and subsequent links. One way to achieve this is to hard code the index in the rx_rst[i] wire in the pattern checker and the synchronizer (j204c_pulse_CDC) instantiations generation loop with rx_rst[0]. Refer to the following figures for the RX reset distribution.
Figure 7. JESD204C RX IP Link Reset
Figure 8. Pattern Checker for the Frame Reset for the Data Channel and Link Reset for the Command Channel
Figure 9. JESD204C RX IP, Data Channel, and Command Channel Pattern Checker Error Flag Synchronizer Reset
Figure 10. Sysref Synchronizer Reset
2. Change the dimension of the following wires. This example is shown in Verilog HDL:
3. Add an index to the following wires at the Platform Designer ports of the JESD204C RX IP. Use index [0] for link 0, index [1] for link 1, and so forth. Example:
1. j204c_rx_dev_lane_align[0]
2. j204c_rx_dev_emblock_align[0]
4. Connect the j204c_rx_dev_lane_align port of each IP to an AND gate. Distribute the output of the AND gate to the j204c_rx_alldev_lane_align port of each IP.
// Example in Verilog
assign j204c_rx_alldev_lane_align = &j204c_rx_dev_lane_align;
5. Connect the j204c_rx_dev_emblock_align port of each IP to an AND gate. Distribute the output of the AND gate to the j204c_rx_alldev_emblock_align port of each IP.
// Example in Verilog
assign j204c_rx_alldev_emblock_align = &j204c_rx_dev_emblock_align;
6. Create the following wires:
7. Connect the rx_pma_ready_in of each link to the input of an AND gate. Connect the output of the AND gate to rx_pma_ready_in_all.
// Example in Verilog
assign rx_pma_ready_in_all = &rx_pma_ready_in;
8. Connect the rx_xcvr_ready_in of each link to the input of an AND gate. Connect the output of the AND gate to rx_xcvr_ready_in_all.
// Example in Verilog
assign rx_xcvr_ready_in_all = &rx_xcvr_ready_in;
9. Replace the rx_pma_ready_in[0] connection at the rst_seq_1_reset2_dsrt_qual_reset2_dsrt_qual port of the Platform Designer system with the output of the AND gate of rx_pma_ready_in_all.
10. Replace the rx_xcvr_ready_in[0] connection at the rst_seq_1_reset3_dsrt_qual_reset3_dsrt_qual port of the Platform Designer system with the output of the AND gate of rx_xcvr_ready_in_all.
11. For the rest of the ports, increase the index wires from 0 to 1, and use subsequent numbers for the subsequent links.
Example: The rx_avst_data[1] wire should be connected to link 1 IP.
5. Connect the j204c_rx_emb_lock output port of each IP to the input of an AND gate. Connect the output of the AND gate to the emb_lock_out output port of the design example. Perform a similar action for the rx_sh_lock port.
// Example in Verilog
assign emb_lock_out = &rx_emb_lock;
assign sh_lock_out = &rx_sh_lock;

6. For subclass 1 subsystem, comment out or delete the sysref_out port and its assignment. SYSREF should be sourced from the clock generator, which supplies the device clock to the ADC and the FPGA. The fpga_sysref signal from ED Control block is meant for debug purpose only.
// Example in Verilog
// output wire sysref_out,
// assign sysref_out = fpga_sysref; 
7. Save the top-level HDL file changes.