AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP

ID 683537
Date 3/26/2023
Document Table of Contents Adding IP Signals to the Simulation Waveform

Note: This is an optional step.

You can add the signals of the IPs to the simulation waveform to monitor the link initialization. For the ModelSim- Intel® FPGA Edition, include the signals of interest into the file in the simulation/mentor folder. Example:

add wave -noupdate -divider {RX LINK 1}

add wave -noupdate /tb_top/u_intel_j204c_ed_rx/u_j204c_rx_ss/j204c_rx_ip/intel_jesd204c_1/j204c_rx_sysref

A sample of the file is included in the design example available at the Design Store.