AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA E-Tile JESD204C RX IP
Visible to Intel only — GUID: mmd1578292172813
Ixiasoft
Visible to Intel only — GUID: mmd1578292172813
Ixiasoft
1.3.1.6. Adding IP Signals to the Simulation Waveform
You can add the signals of the IPs to the simulation waveform to monitor the link initialization. For the ModelSim- Intel® FPGA Edition, include the signals of interest into the tb_top_waveform.do file in the simulation/mentor folder. Example:
add wave -noupdate -divider {RX LINK 1} add wave -noupdate /tb_top/u_intel_j204c_ed_rx/u_j204c_rx_ss/j204c_rx_ip/intel_jesd204c_1/j204c_rx_sysref
A sample of the tb_top_waveform.do file is included in the design example available at the Design Store.