AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel® Agilex™ FPGA E-Tile JESD204C RX IP

ID 683537
Date 9/21/2020
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Document Table of Contents
Document Table of Contents
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel® Agilex™ FPGA E-Tile JESD204C RX IP
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel® Agilex™ FPGA E-Tile JESD204C RX IP
1.1. ADC to Intel® Agilex™ Dual Link Design Overview 1.2. ADC to Intel® Agilex™ Dual Link Design Implementation Guidelines 1.3. Synchronized ADC to Intel® Agilex™ Dual Link 1.4. Downloading and Operating the Design Example 1.5. Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel® Agilex™ FPGA E-Tile JESD204C RX IP
1.3. Synchronized ADC to Intel® Agilex™ Dual Link
1.3.1. Design Simulation Guidelines 1.3.2. Design Synthesis Guidelines
1.3.1. Design Simulation Guidelines
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel® Agilex™ Dual Link 1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel® Agilex™ Dual Link 1.3.1.3. Editing TX Simulation Model Platform Designer System for Synchronized ADC to Intel® Agilex™ Dual Link 1.3.1.4. Editing TX Simulation Model Top-Level HDL for Synchronized ADC to Intel® Agilex™ Dual Link 1.3.1.5. Editing Simulation Testbench for Synchronized ADC to Intel® Agilex™ Dual Link 1.3.1.6. Adding IP Signals to the Simulation Waveform 1.3.1.7. Updating the Simulation Script 1.3.1.8. Simulating the Dual Link Design 1.3.1.9. Viewing the Simulation Results
1.3.2. Design Synthesis Guidelines
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel® Agilex™ Dual Link 1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel® Agilex™ Dual Link 1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Intel® Agilex™ Dual Link 1.3.2.4. Compiling the Design in Intel® Quartus® Prime Software
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel® Agilex™ FPGA E-Tile JESD204C RX IP

1.3.1.6. Adding IP Signals to the Simulation Waveform

Note: This is an optional step.

You can add the signals of the IPs to the simulation waveform to monitor the link initialization. For the ModelSim- Intel® FPGA Edition, include the signals of interest into the tb_top_waveform.do file in the simulation/mentor folder. Example: 

add wave -noupdate -divider {RX LINK 1}

add wave -noupdate /tb_top/u_intel_j204c_ed_rx/u_j204c_rx_ss/j204c_rx_ip/intel_jesd204c_1/j204c_rx_sysref

A sample of the tb_top_waveform.do file is included in the design example available at the Design Store.

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