AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel® Agilex™ FPGA E-Tile JESD204C RX IP

ID 683537
Date 9/21/2020
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1.3.2.4. Compiling the Design in Intel® Quartus® Prime Software

After modifying the Platform Designer system, top-level HDL file, Quartus setting file, and top-level SDC constraint file, compile the design with the Intel® Quartus® Prime software. Intel® recommends that you perform Analysis and Synthesis and use the RTL Viewer to check the correctness of the connections before fully compiling your dual link design.

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