AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP

ID 683537
Date 3/26/2023
Document Table of Contents

1.4. Downloading and Operating the Design Example

The design example has L=4, M=8, and F=4 configurations from the JESD204C Intel® FPGA IP preset. This design example is verified using simulation, and no hardware testing is performed. The top-level design file is a synthesis design that is migrated from the simulation design. The simulation folder contains the simulation design. The rtl folder contains the RX dual link design and the simulation/models/j204c_tx folder contains the link partner TX dual link design.

Follow these steps to download and operate the design example:
  1. Download the design example file (.par) from Design Store and restore the design using Intel® Quartus® Prime Pro Edition software version 20.1 and above.
  2. In the Intel® Quartus® Prime Pro Edition software, click File > Open Project to extract the .par design example.

The .par file includes and README.txt files.

  1. Extract the files and folders from the file into simulation folder. Place the simulation folder at the directory structure as described in the Readme.txt file.
    Note: The directory structure of the design example in the Design Store is different from the directory structure of the design example generated by the Intel® Quartus® Prime Pro Edition software. Refer to the README.txt file for more details about the directory structure.
  2. Follow the instructions in the Simulating the Dual Link Design section.

The explanations of the simulation results are presented in the Viewing the Simulation Results section.