18.104.22.168. Editing Design Example Platform Designer System for Synchronized ADC to Intel® Agilex™ Dual Link
- Open the Intel® Quartus® Prime project of the generated design example, intel_j204c_ed_rx.qpf, in the ed/quartus/ folder.
- Open the top-level system, j204c_rx_ss.qsys, in Platform Designer. The RX .qsys file is located in the ed/rtl/rx/ folder.
- In the System View tab, right-click the j204c_rx_ip instance, and select Drill into Subsystem. This opens the j204c_rx_ip Platform Designer subsystem.
- Right-click the intel_jesd204c component, and select Duplicate.
This duplicates the JESD204C Intel® FPGA IP. Rename the duplicated IP as intel_jesd204c_1.Note: Select No if the Platform Designer prompts the following: Do you want to also duplicate the IP Variant file on the disk? This is because the duplicated JESD204C Intel® FPGA IP has the same parameters as the original JESD204C Intel® FPGA IP.
- Export all JESD204C Intel® FPGA IP ports except for the j204c_tx2rx_lbdata port.
- Move up one level of the hierarchy to j204c_rx_ss; this is the top level of the Platform Designer system.
- Connect the duplicated IP port as shown in the following table:
Ports for Duplicated IP Connection j204c_rx_phy_rst_n rst_seq_1.reset_out0 j204c_pll_refclk refclk_xcvr.out_clk 4 j204c_reconfig_clk mgmt_clk.out_clk j204c_reconfig_reset reset_controller_0.reset_out j204c_reconfig
j204c_rx_avs_clk mgmt_clk.out_clk j204c_rx_avs_rst_n rst_seq_1.reset_out0 j204c_rx_avs mm_bridge.m0 j204c_rxlink_clk ed_control.rxlink_clk j204c_rxframe_clk rxframe_clk.out_clk
- Change the connection of the j204c_rx_avs_rst_n port of the original JESD204C IP to rst_seq_1.reset_out0.
Note: You can assert the Avalon® memory-mapped interface reset for the IP control and status register (CSR) at the same time as the PHY reset. Refer to the JESD204C TX/RX Reset Sequence figure in the JESD204C Intel® FPGA IP User Guide.
- Export the rest of the ports by clicking on the Double-click to export in the Export column of the System View tab.
- At the address map, adjust the starting address of the j204c_rx_avs and j204c_reconfig interfaces so that there is no conflict with other components or interfaces. For example, you can set the starting address of intel_jesd204c_1 IP to 0x000d_0400 as shown in the following table:
Table 4. Synchronized ADC-FPGA Dual Link Address Map for Design Example with System Console Control jtag_avmm_bridge.master mm_bridge.m0 j204c_rx_ip.intel_jesd204c_j204c_rx_avs N/A 0x000d_0000 – 0x000d_03ff j204c_rx_ip.intel_jesd204c_1_j204c_rx_avs N/A 0x000d_0400 – 0x000d_07ff j204c_rx_ip.intel_jesd204c_j204c_reconfig 0x0200_0000 – 0x021f_ffff 5 N/A j204c_rx_ip.intel_jesd204c_1_j204c_reconfig 0x0220_0000 – 0x023f_ffff 5 N/A
- Repeat step 4 through step 10 for subsequent links in your design.
- Click Generate HDL to generate the design files needed for Intel® Quartus® Prime compilation.
- Click Generate and Yes to save and generate the design files.
- After the HDL generation is completed, select Generate from the menu. Select Show Instantiation Template…, and click Copy.
- Paste the instantiation template of j204c_rx_ss Platform Designer into a text editor.
You must update the instantiated Platform Designer ports at the top-level HDL.
- After the HDL generation is completed, click Finish to save your Platform Designer settings, and exit the Platform Designer window.
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