Skip To Main Content
Intel logo - Return to the home page
My Tools

Select Your Language

  • Bahasa Indonesia
  • Deutsch
  • English
  • Español
  • Français
  • Português
  • Tiếng Việt
  • ไทย
  • 한국어
  • 日本語
  • 简体中文
  • 繁體中文
Sign In to access restricted content

Using Intel.com Search

You can easily search the entire Intel.com site in several ways.

  • Brand Name: Core i9
  • Document Number: 123456
  • Code Name: Emerald Rapids
  • Special Operators: “Ice Lake”, Ice AND Lake, Ice OR Lake, Ice*

Quick Links

You can also try the quick links below to see results for most popular searches.

  • Product Information
  • Support
  • Drivers & Software

Recent Searches

Sign In to access restricted content

Advanced Search

Only search in

Sign in to access restricted content.
  1. Intel® Products
  2. Altera® FPGA, SoC FPGA and CPLD
  3. Altera® FPGA Intellectual Property
  4. Interface Protocols IP Cores
  5. JESD204 FPGA IP Overview

The browser version you are using is not recommended for this site.
Please consider upgrading to the latest version of your browser by clicking one of the following links.

  • Safari
  • Chrome
  • Edge
  • Firefox

JESD204 FPGA IP

The JEDEC committee created the JESD204 data converter serial interface standard to standardize and reduce the number of data inputs/outputs between high-speed data converters and other devices, such as FPGAs. The protocol has many advantages, such as simplified layouts, skew management, and deterministic latency.

High Performance and Easy Integration

Altera JESD204 IP simplifies the integration of high-speed data converters with digital processing systems. The IP supports data rates as high as 32.44 Gbps and manages the physical, data link, and transport layers while simplifying configuration, clock synchronization, and data transmission.

IP is pre-verified and JEDEC Compliant which is crucial for ensuring interoperability and reliability in high-speed data applications. The IP includes design examples simplifying integration and enabling ease-of-use reducing development time for designers.

  • Data Rates and Features
  • Interoperability Reports
  • Documentation
  • Applications
  • Ordering Information
IP Protocol Features Agilex™ 7 FPGA (E-Tile)

Agilex™ 7 FPGA (F-Tile)

Agilex™ 9 FPGA (F-Tile)

Agilex™ 5 FPGA E-Series (GTS) Device B Agilex™ 5 FPGA E-Series (GTS) Device A Agilex™ 5 FPGA D-Series (GTS) Agilex™ 3 FPGA 
JESD204C Max Data Rate 28.9 Gbps 32.44032 Gbps 17.16 Gbps 28.1 Gbps -
Lanes 1-16x  1-8x -
Data Modes

Simplex (TX-only, RX-only)

Duplex (TX/RX- Shared PHY, Same Data Rates)

Simplex (TX-only, RX-only)

Duplex (TX/RX- Shared PHY, Same Data Rates)

Dual Simplex (TX/RX – Independent PHY, Different Data Rates)

-
JESD204B Max Data Rate 19.2 Gbps 20 Gbps 17.1 Gbps 20 Gbps 20 Gbps 12.5 Gbps
Lanes 1-8x 1-8x 1-4x
Data Modes

Simplex (TX-only, RX-only)

Duplex (TX/RX- Shared PHY, Same Data Rates)

Simplex (TX-only, RX-only)

Duplex (TX/RX- Shared PHY, Same Data Rates)

Dual Simplex (TX/RX – Independent PHY, Different Data Rates)

View all Show less

Note: For detailed IP information check the respective IP user guides in the documentation section.

Additional Resources

Find IP

Find the right Altera® FPGA Intellectual Property core for your needs.

Technical Support

For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.

IP Evaluation and Purchase

Evaluation mode and purchasing information for Altera® FPGA Intellectual Property cores.

IP Base Suite

Free Altera® FPGA IP Core licenses with an active license for Quartus® Prime Standard or Pro Edition Software.

Design Examples

Download design examples and reference designs for Altera® FPGA devices.

Contact Sales

Get in touch with sales for your Altera® FPGA product design and acceleration needs.

Show more Show less
IP Protocol Agilex ™ 7 FPGA (E-Tile)

Agilex ™ 7 FPGA (F-Tile)

Agilex™ 9 FPGA (F-Tile)

JESD204C AN 960: Interoperability Report with ADI AD9081 MxFE* ADC

AN 876: Interoperability Report with ADI AD9081 MxFE* ADC

AN 976: Interoperability Report with ADI AD9081 MxFE* DAC

View all Show less
IP Protocol Agilex ™ 7 FPGA (E-Tile)

Agilex ™ 7 FPGA (F-Tile)

Agilex™ 9 FPGA (F-Tile)

Agilex™ 5 FPGA (GTS)
JESD204C E-Tile JESD204C FPGA IP User Guide F-Tile JESD204C FPGA IP User Guide GTS JESD204C FPGA IP User Guide
E-Tile JESD204C Agilex 7 Design Example User Guide F-Tile JESD204C FPGA IP Design Example User Guide  GTS JESD204C FPGA IP Design Example User Guide
E-Tile JESD204C FPGA IP Release Notes F-Tile JESD204C FPGA IP Release Notes GTS JESD204C FPGA IP Release Notes
JESD204B E-Tile JESD204B FPGA IP User Guide F-Tile JESD204B FPGA IP User Guide GTS JESD204B FPGA IP User Guide
E-Tile JESD204B Agilex 7 Design Example User Guide F-Tile JESD204B FPGA IP Design Example User Guide GTS JESD204B FPGA IP Design Example User Guide
E-Tile JESD204B FPGA IP Release Notes F-Tile JESD204B FPGA IP Release Notes GTS JESD204B FPGA IP Release Notes
View all Show less

JESD204 IP Integration Documentation

  • AN 901: Implementing ADC Dual Link Design with Agilex™ 7 FPGA E-Tile JESD204C RX IP
  • AN 967: Multiple Device Synchronization in Digital Phased Array System
  • Multiple Device Synchronization for Agilex® 9 SoC FPGA Direct RF-Series

Related Links

JESD204 FPGA IP Resource Page

  • Wireless Communications
    • Learn about the complete solution for rapid deployment of 5G Open RAN O-RU workloads
  • Radar and Defense Systems
    • Learn how Agilex™ 9 SoC FPGAs use JESD204C protocol to support multiple device synchronization
  • Medical Imaging
    • Learn about Agilex™ 5 Medical Imaging and Client Systems workloads
  • Broadcast
  • Test and Measurement Equipment
IP License Ordering Code
JESD204 FPGA IP Suite
Primary: IPS-JESD204
Renewal: IPSR-JESD204
Note: Purchase and renewal of JESD204 FPGA IP Suite will include the following IP licenses: IP-JESD204C, IP-JESD204C-FTILE, IP-JESD204B, IP-JESD204B-FTILE
View all Show less
Compare Products
  • Company Overview
  • Contact Intel
  • Newsroom
  • Investors
  • Careers
  • Corporate Responsibility
  • Inclusion
  • Public Policy
  • © Intel Corporation
  • Terms of Use
  • *Trademarks
  • Cookies
  • Privacy
  • Supply Chain Transparency
  • Site Map
  • Recycling
  • Your Privacy Choices California Consumer Privacy Act (CCPA) Opt-Out Icon
  • Notice at Collection

Intel technologies may require enabled hardware, software or service activation. // No product or component can be absolutely secure. // Your costs and results may vary. // Performance varies by use, configuration, and other factors. Learn more at intel.com/performanceindex. // See our complete legal Notices and Disclaimers. // Intel is committed to respecting human rights and avoiding causing or contributing to adverse impacts on human rights. See Intel’s Global Human Rights Principles. Intel’s products and software are intended only to be used in applications that do not cause or contribute to adverse impacts on human rights.

Intel Footer Logo