JESD204 FPGA IP

The JEDEC committee created the JESD204 data converter serial interface standard to standardize and reduce the number of data inputs/outputs between high-speed data converters and other devices, such as FPGAs. The protocol has many advantages, such as simplified layouts, skew management, and deterministic latency.

High Performance and Easy Integration

Altera JESD204 IP simplifies the integration of high-speed data converters with digital processing systems. The IP supports data rates as high as 32.44 Gbps and manages the physical, data link, and transport layers while simplifying configuration, clock synchronization, and data transmission.

IP is pre-verified and JEDEC Compliant which is crucial for ensuring interoperability and reliability in high-speed data applications. The IP includes design examples simplifying integration and enabling ease-of-use reducing development time for designers.

IP Protocol Features Agilex ™ 7 FPGA (E-Tile)

Agilex ™ 7 FPGA (F-Tile)

Agilex™ 9 FPGA (F-Tile)

 Agilex™ 5 FPGA E-Series (GTS) Device Group B Agilex™ 5 FPGA E-Series (GTS) Device Group A Agilex™ 5 FPGA D-Series (GTS) Agilex™3 FPGA 
JESD204C Max Data Rate 28.9 Gbps 32.44032 Gbps 17.16 Gbps 28.1 Gbps  
Lanes 1-16x  1-8x
Data Modes 

Simplex (TX-only, RX-only)

Duplex (TX/RX- Shared PHY, Same Data Rates)

Simplex (TX-only, RX-only)

Duplex (TX/RX- Shared PHY, Same Data Rates)

Dual Simplex (TX/RX – Independent PHY, Different Data Rates)
JESD204B Max Data Rate 19.2 Gbps 20 Gbps 17.1 Gbps 20 Gbps 20 Gbps 12.5 Gbps
Lanes 1-8x 1-8x 1-4x
Data Modes

Simplex (TX-only, RX-only)

Duplex (TX/RX- Shared PHY, Same Data Rates)

Simplex (TX-only, RX-only)

Duplex (TX/RX- Shared PHY, Same Data Rates)

Dual Simplex (TX/RX – Independent PHY, Different Data Rates)
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Note: For detailed IP information check the respective IP user guides in the documentation section.

IP Protocol Agilex ™ 7 FPGA (E-Tile)

Agilex ™ 7 FPGA (F-Tile)

Agilex™ 9 FPGA (F-Tile)
JESD204C AN 960: Interoperability Report with ADI AD9081 MxFE* ADC AN 876: Interoperability Report with ADI AD9081 Mx FE* ADC

AN 976: Interoperability Report with ADI AD9081 MxFE* DAC

 
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IP Protocol Agilex ™ 7 FPGA (E-Tile)

Agilex ™ 7 FPGA (F-Tile)

Agilex™ 9 FPGA (F-Tile)

 Agilex™ 5 FPGA (GTS)
JESD204C E-Tile JESD204C FPGA IP User Guide F-Tile JESD204C FPGA IP User Guide GTS JESD204C FPGA IP User Guide
E-Tile JESD204C Agilex 7 Design Example User Guide F-Tile JESD204C FPGA IP Design Example User Guide  GTS JESD204C FPGA IP Design Example User Guide
E-Tile JESD204C FPGA IP Release Notes F-Tile JESD204C FPGA IP Release Notes GTS JESD204C FPGA IP Release Notes
JESD204B E-Tile JESD204B FPGA IP User Guide F-Tile JESD204B FPGA IP User Guide GTS JESD204B FPGA IP User Guide
E-Tile JESD204B Agilex 7 Design Example User Guide F-Tile JESD204B FPGA IP Design Example User Guide GTS JESD204B FPGA IP Design Example User Guide
E-Tile JESD204B FPGA IP Release Notes F-Tile JESD204B FPGA IP Release Notes GTS JESD204B FPGA IP Release Notes
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Ordering Codes and Pricing

After you have purchased the license for the JESD204 FPGA IP Suite, you can obtain and manage the license through the Self-Service Licensing Center.

For more information, visit the Licensing Support Center

IP Ordering Code Primary Renewal
JESD204 FPGA IP Suite
 Primary: IPS-JESD204
Renewal: IPSR-JESD204

Digikey

Mouser

Arrow

Digikey

Mouser
Note: Purchase and renewal of JESD204 FPGA IP Suite will include the following IP licenses: IP-JESD204C, IP-JESD204C-FTILE, IP-JESD204B, IP-JESD204B-FTILE
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