AN 967: Multiple Device Synchronization in Digital Phased Array System

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ID 734485
Date 12/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Digital Phased Array Synchronization 3. Multiple Device Synchronization in DPA System 4. Test Result 5. Conclusion 6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System A. Appendix
3. Multiple Device Synchronization in DPA System x
3.1. JESD204(A/B/C) Interface 3.2. Clock/SYSREF Scheme 3.3. FPGA Design Synchronization 3.4. Data Exchange between FPGA Devices 3.5. Event Trigger Synchronization
3.2. Clock/SYSREF Scheme x
3.2.1. clk_ref 3.2.2. clk_dev and SYSREF 3.2.3. SYSREF Capture
3.3. FPGA Design Synchronization x
3.3.1. Data and SYSREF Clock Domain Crossing 3.3.2. Data Transformation when Clock Domain Crossing
3.5. Event Trigger Synchronization x
3.5.1. SYSREF Distribution
A. Appendix x
A.1. FPGA I/O Timing Constraints for SYSREF
A.1. FPGA I/O Timing Constraints for SYSREF x
A.1.1. Source-Synchronous Interface Timing Constraints A.1.2. SYSREF I/O Timing Closure
A.1.2. SYSREF I/O Timing Closure x
A.1.2.1. Adjust Input Delay Chain Value A.1.2.2. Using PLL to Adjust clk_dev Phase A.1.2.3. Place First SYSREF Capture Register in IOE
1. Introduction
2. Digital Phased Array Synchronization
3. Multiple Device Synchronization in DPA System
4. Test Result
5. Conclusion
6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System
A. Appendix

1. Introduction

This document provides guidelines for multiple data converters and FPGA devices system synchronization in the Digital Phased Array (DPA) system.

This document focuses on:

  • Implementation of JESD204B/C with the deterministic latency
  • Clock and SYSREF scheme
  • Data transformation in clock domain crossing
  • Event trigger synchronization

You must be familiar with JESD204B/C protocol and JESD204B/C Intel® FPGA IP core.

Table 1.  Related Documents
Reference Description
JESD204B Intel® FPGA IP User Guide Provides the features, architecture description, steps to instantiate, and guidelines to design the F-Tile JESD204C Intel® FPGA IP using Intel Agilex® 7, Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Stratix® V devices.
JESD204C Intel® FPGA IP User Guide Provides the features, architecture description, steps to instantiate, and guidelines to design the F-Tile JESD204C Intel® FPGA IP using Intel Agilex® 7, and Intel® Stratix® 10 devices.
F-Tile JESD204C Intel® FPGA IP User Guide Provides the features, architecture description, steps to instantiate, and guidelines to design the F-Tile JESD204C Intel® FPGA IP using Intel Agilex® 7 devices.
F-Tile JESD204B Intel® FPGA IP User Guide Provides the features, usage guidelines, and detailed description about the design examples for the F-Tile JESD204B Intel® FPGA IP using Intel Agilex® 7 devices.
AN 433: Constraining and Analyzing Source-Synchronous Interfaces Describes techniques for constraining and analyzing source-synchronous interfaces.
Table 2.  Terms and AcronymsThe following is a list of acronyms used throughout this document.
Acronym Expansion
ADC Analog to Digital Data Converter
AIB Advanced Interface Bus
DPA Digital Phased Array
DDR Double Data Rate
FIFO First-In-First-Out
I/O Input/Output
IOE Input/Output Element
PA Phased Array
PCB Printed Circuit Board
PVT Process, Voltage and Temperature
RX Receiver
TX Transmitter
Level Two Title