AN 967: Multiple Device Synchronization in Digital Phased Array System

ID 734485
Date 12/15/2023

A.1.2.2. Using PLL to Adjust clk_dev Phase

If the timing is still not met after adjusting the delay of the programmable input delay chain, you can use a PLL to shift the clk_dev phase and use the PLL output clock to capture the SYSREF as shown in the following figure.
Figure 20. PLL Provides Clock Shift

If PLL is used to provide the phase shift for clk_dev, you do not need to adjust the delay of the programmable input delay chain. Instead, set the input delay chain value to 0. Additionally, place the first SYSREF capture register in the IOE to reduce the trace delay from I/O pin to the register input. All these operations aim at reducing the delta part of the delay in different PVT, making it easier to meet timing in all the timing models, across different voltage, and temperature variations.