AN 967: Multiple Device Synchronization in Digital Phased Array System

ID 734485
Date 12/15/2023

3.5.1. SYSREF Distribution

Many different system events are triggered by SYSREF. However, there is only one SYSREF signal connected to FPGA in most cases. Consequently, you need to distribute SYSREF internally inside FPGA.

The following figure shows the SYSREF capture and distribution logic.

Figure 15. SYSREF Capture and Distribution

The SYSREF distributor copies the recovered sysref_rcvd to its outputs based on the SYSREF_mask signal. The SYSREF_mask signal width equals to the number of the output ports. Each bit controls whether to copy SYSREF to the corresponding output port. Multiple bits of the SYSREF_mask signal can be set to copy SYSREF to multiple output ports. However, in most cases, SYSREF_mask is a one-hot signal and only one output port can receive SYSREF.