AN 967: Multiple Device Synchronization in Digital Phased Array System

ID 734485
Date 12/15/2023
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3.2.2. clk_dev and SYSREF

In the JESD204B Intel® FPGA IP and JESD204C Intel® FPGA IP, clk_dev is the device clock generated by clock device that is used as the clock source for the FPGA device as well as driving the digital circuit and I/O operations of the data converter. In Intel JESD204B/C IP, clk_dev is used to generate transceiver PLL reference clock and core PLL reference clock. clk_dev and SYSREF pair for data converters and FPGA are precisely routed to match the delay and guarantees the setup time and hold time are met for all the components.

The increasing sample speeds of data converters and the drift of voltage/temperature makes it challenging to satisfy the setup and hold time through the PCB trace delay control. Intel recommends that you use the clock devices which supports the adjustable delay of the outputs in the clock circuit.

If the SYSREF has a timing violation at the data converter or FPGA I/O, it might be captured by the wrong clk_dev edge, causing a whole clock cycle misalignment. This captured uncertainty prevents deterministic latency across the system.

The following figure shows four ADC waveforms in an event where a SYSREF is captured by the wrong clk_dev edge. The channel with the SYSREF captured by the wrong clk_dev edge has one clk_dev clock cycle skew when comparing with other channels, but the waveforms are still clean and smooth because the clk_ref signals are coherent and synchronized.

Figure 7. ADC Waveforms when SYSREF Captured by Wrong clk_dev Edge