3.2.2. clk_dev and SYSREF
The increasing sample speeds of data converters and the drift of voltage/temperature makes it challenging to satisfy the setup and hold time through the PCB trace delay control. Intel recommends that you use the clock devices which supports the adjustable delay of the outputs in the clock circuit.
If the SYSREF has a timing violation at the data converter or FPGA I/O, it might be captured by the wrong clk_dev edge, causing a whole clock cycle misalignment. This captured uncertainty prevents deterministic latency across the system.
The following figure shows four ADC waveforms in an event where a SYSREF is captured by the wrong clk_dev edge. The channel with the SYSREF captured by the wrong clk_dev edge has one clk_dev clock cycle skew when comparing with other channels, but the waveforms are still clean and smooth because the clk_ref signals are coherent and synchronized.