AN 967: Multiple Device Synchronization in Digital Phased Array System

ID 734485
Date 12/15/2023
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3.3.1. Data and SYSREF Clock Domain Crossing

In the FPGA design, clock domain crossing causes latency misalignment. For example, when the data goes through a FIFO, the latency varies during the start condition of the FIFO status, which changes in each power cycle.

However, clock domain crossing is required in the FPGA design. For example, for JESD204C Intel FPGA IP core, TX/RX link_clock = line rate/132.

The maximum line rate for Intel® Stratix® 10 (E-Tile) devices is 28.9 Gbps, so the maximum link_clock frequency = 28.9 Gbps/132 = 218.94 MHz .

Intel® Stratix® 10 FPGA devices can run at a higher frequency with narrower data width to reduce the resource usage. This requires clock domain crossing between link_clock and frame_clock.

You must be careful with the clock domain crossing to avoid latency uncertainty. Typically, frame_clock frequency is a multiple of link_clock frequency. When data is transferred between frame_clock and link_clock domains, the destination clock captures the data directly. You must set a correct setup or hold relationship in the timing constraint script and check the timing analysis report to confirm that there is no timing violation.

You must not set a false path between link_clock and frame_clock in the timing analyzer, because these paths must be analyzed. For other modules, a false path is needed to be set between these two clock domains. You must use the node name to set the false path for the particular paths.

This requirement is also applicable to SYSREF clock domain crossing.