AN 967: Multiple Device Synchronization in Digital Phased Array System

ID 734485
Date 12/15/2023
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A.1.2.1. Adjust Input Delay Chain Value

There is a programmable delay chain in the IOE. You can set the delay value in Quartus -> Assignment Editor, as shown in the following figure. The sysref_in is the SYSREF pin name in FPGA project.
Figure 19. Input Delay Chain Setting

The value 0 means minimum delay. Increasing the delay value increases the physical delay of the delay chain.

After changing the programmable input delay chain value, you must re-compile the FPGA project and check the I/O timing again. It needs several iterations to find the suitable delay value.

Intel recommends that you set the delay value as small as possible. A smaller delay has a smaller delta part in different PVT, making it easier to meet timing in different timing models.