AN 967: Multiple Device Synchronization in Digital Phased Array System

ID 734485
Date 12/15/2023

A.1.2. SYSREF I/O Timing Closure

If you apply the correct I/O timing constraints to SYSREF, the FPGA compiler intends to meet the I/O timing requirement during compilation. However, the I/O timing may still fail when the I/O timing requirement is difficult to meet. Consequently, you can adjust the input delay chain value manually, adjust the clk_dev phase by a PLL, or place the first stage SYSREF capture register in the IOE.