3.3.2. Data Transformation when Clock Domain Crossing
link_clock is the timing reference for the JESD204B/C Intel® FPGA IP core. For the JESD204B Intel® FPGA IP core, the link_clock runs at data rate/40 because the IP core operates in a 32-bit data bus architecture after 8B/10B encoding. For the JESD204C Intel® FPGA IP core, the link_clock is line rate divided by 132 because the link_clock operates in a 132-bit data bus domain architecture after 64B/66B encoding. For the JESD204B/C subclass 1, to avoid half link clock latency variation, you must supply the clk_dev at the same frequency as the link_clock.
frame_clock is the clock of the user logic in FPGA.
In Data and SYSREF Clock Domain Crossing, it states that frame_clock frequency is a multiple of the link_clock frequency. When data is transferred from the frame_clock domain to the link_clock domain, multiple clock cycles’ data are merged into a single beat wider data in the link_clock domain. Conversely, when data is transferred from the link_clock domain to the frame_clock domain, wider data is split into narrower data and assigned to different frame_clock cycles.
The following figure shows an example of data transformation from the link_clock domain to the frame_clock domain. The frame_clock to link_clock frequency ratio is 2:1. The phase_clock is generated by the same PLL as link_clock but with a 90 degree phase shift. It is used to locate the boundary of the link_clock data.
The following figure shows an example of data transformation from the frame_clock domain to the link_clock domain. The link_clock to frame_clock frequency ratio is 1:2.
The following figure shows the link_clock, frame_clock, and phase_clock that need to be generated by the same PLL, based on clk_dev.